About The SweRV Core EH2

Checking out a new dual threaded commercial RISC-V core for IoT, artificial intelligence and data-intensive embedded applications.


In mid-May, CHIPS Alliance announced the open sourcing of the SweRV Core EH2 and SweRV Core EL2 designed by Western Digital. These cores, as well as the earlier EH1, are now supported by Codasip’s SweRV Core Support Package which provides all of the components necessary to design, implement, test, and write software for a SweRV Core-based system-on-chip. But what is SweRV Core EH2?

The SweRV Core EH1 was the first to be released through CHIPS Alliance and was a core aimed at high-end embedded applications including Western Digital’s flash controllers and SSDs. The core is a dual issue, superscalar, high-performance core with 9 pipeline stages. The EH2 is an exciting further development aimed at delivering even more performance for IoT, artificial intelligence and data-intensive embedded applications.

The EH2 breaks new ground for RISC-V cores by being the world’s first dual threaded, commercial RISC-V core. Its 9-stage pipeline is based on that of the EH1, but it contains additional resources to support dual threading. There are doubled RISC-V general purpose registers, control and status registers, fetch buffers, instruction buffers, and other logic. By adding these incremental resources, the EH2 allows the host software to effectively ‘see two cores.’ The simulated performance of the dual threaded EH2 core is an outstanding 6.3 CoreMark/MHz.

The SweRV Core EH2 supports machine mode only, meaning that it is aimed at applications using real-time operating systems or bare metal software. It has four 64-bit AXI4 bus interfaces for instruction fetch, load/stores, debug, and for accessing optional closely coupled memories. There is an optional instruction cache with either parity-based or ECC-based error protection, an optional instruction closely coupled memory (ICCM), and an optional data closely coupled memory (DCCM) which use ECC-based error protection.

The open-source RTL for the SweRV Core EH2 is available from CHIPS Alliance. However, considerably more than just RTL is needed to integrate the core into a system-on-chip (SoC) and to develop the associated firmware. A considerable amount of effort will be needed to create the EDA flows in particular and to maintain them over multiple RTL and EDA software versions.

The SweRV Core Support Package (SCSP) contains everything needed to deploy a Western Digital SweRV EH2 core in an integrated circuit, providing support for both EDA tool flows and embedded software development. SCSP saves the considerable effort that would be needed to set up EDA flows for the EH2 core from scratch. The SweRV Core Support Package for EH2 is available in both basic Free and Pro versions.

The Free version consists of open-source deliverables and infrastructure for using open-source EDA tools and an SDK. Users can access an internet forum for support.

The Pro version combines open-source and commercial deliverables. It provides flows, examples and models for using commercial EDA tools. This version includes professional support by e-mail and telephone.

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