Open-Source Hardware Momentum Builds


Open-source hardware continues to gain ground, spearheaded by RISC-V — despite the fact that this processor technology is neither free nor simple to use. Nevertheless, the open-source hardware movement has established a solid foothold after multiple prior forays that yielded only limited success, even for processors. With demand for more customized hardware, and a growing field of startups... » read more

About The SweRV Core EH2


In mid-May, CHIPS Alliance announced the open sourcing of the SweRV Core EH2 and SweRV Core EL2 designed by Western Digital. These cores, as well as the earlier EH1, are now supported by Codasip’s SweRV Core Support Package which provides all of the components necessary to design, implement, test, and write software for a SweRV Core-based system-on-chip. But what is SweRV Core EH2? ... » read more

Simplifying And Speeding Up Verification


Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; Nasr Ullah, senior director of performance architecture at SiFive. What follows are excerpt... » read more

The Increasingly Ordinary Task Of Verifying RISC-V


As RISC-V processor development matures and its usage in SoCs and microcontrollers grows, engineering teams are starting to look beyond the challenges of the processor core itself. So far, the majority of industry verification efforts have focused on ISA compliance to standardize the RISC-V core. Now the focus is shifting to be how to handle verification as the system grows, especially as this... » read more

Week In Review: Auto, Security, Pervasive Computing


Security Ninety-one percent of commercial applications contain outdated or abandoned open-source components —a security threat, says Synopsys in its recently released report 2020 Open Source Security and Risk Analysis (OSSRA). In the fifth annual edition of the report, Synopsys’ research team in its Cybersecurity Research Center (CyRC) found that 99% of the 1,250 commercial codebases revie... » read more

The Hidden Costs of Open Source


It is often implied that if you use an open source processor core there are no costs associated with using it. Of course, the RTL may be free of a license fee and royalties and it might be possible to access a free of charge toolchain for RISC-V, but there are plenty of hidden costs associated with using the core in a real integrated circuit design. If you are using the core in a product... » read more

A New Breed Of Engineer


The industry loves to move in straight lines. Each generation of silicon is more-or-less a linear extrapolation of what came before. There are many reasons for this – products continue to evolve within the industry, adding new or higher performance interfaces, risk levels are lower when the minimum amount is changed for any chip spin, existing software is more likely to run with only minor mo... » read more

Making Sure RISC-V Designs Work As Expected


The RISC-V instruction set architecture is attracting attention across a wide swath of markets, but making sure devices based on the RISC-V ISA work as expected is proving as hard, if not harder, than other commercially available ISA-based chips. The general consensus is that open source lacks the safety net of commercially available IP and tools. Characterization tends to be generalized, ra... » read more

Open Source Faces Challenges In 2020


I recently wrote a couple of posts about open-source EDA tools, OpenROAD: Open-Source EDA from RTL to GDSII and 2nd WOSET Workshop on Open-Source EDA. I have also written about open-source in general, as an approach to development and an approach to business in a post from over four years ago that I think stands up well: The Paradox of Open Source. The reason I called it a paradox is that ... » read more

RISC-V Challenges And Opportunities


Semiconductor Engineering sat down to discuss open instruction set hardware and the future of RISC-V with Ben Levine, senior director of product management in Rambus' Security Division; Jerry Ardizzone, vice president of worldwide sales at Codasip; Megan Wachs, vice president of engineering at SiFive; and Rishiyur Nikhil, CTO of Bluespec. What follows are excerpts of that conversation. (L-... » read more

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