Accelerating Moore’s Law

By Ed Sperling
Ever since the inception of Moore’s Law, process nodes have moved forward at a rate of once every 18 to 24 months. Companies have been talking about slowing down the rate of progression as things get harder, but at least for the next couple of process nodes something very strange will occur—Moore’s Law will accelerate.

The root cause is growing competition for a shrinking number of increasingly valuable and complex SoCs reaching tapeout. The race between Intel, TSMC and the Common Platform triumvirate of IBM, Samsung and Global Foundries shifted into high gear when Intel introduced finFETs at 22nm. That was followed by promises of finFETs by GlobalFoundries and TSMC at 14nm, and later revised to add 14nm finFETs using 20nm back-end of line processes.

FinFETs offer clear advantages for controlling leakage over planar transistors. At the same time, because there is less heat being generated and batteries last longer on mobile devices, the clock frequencies can be turned up for some critical components without overstepping the system power budget. In grossly over-simplified terms, if you save in one place, you can spend in another without altering the balance. Nothing is ever quite that easy, of course, but with some place and route modifications and double patterning issues taken into account, the power/performance improvements that are possible with finFETS—and the carbon-nanotube and tunnel FETs that will follow—are game-changing.

Let the games begin
Intel stunned its competition when it rolled out its “TriGate” version of finFETs at 22nm. And with Intel touting its own limited foundry model to a select few high-volume customers, rival foundries had little choice but to accelerate their own R&D. They appear to have done this quite effectively—in fact the next node will follow introduction of the hybrid node 20/14nm node with FinFETs within about a year.

“In 2013 you will see a model shift,” said Michael Cadigan, general manager of IBM’s microelectronics division. “The focus is on more and earlier involvement, and we will deliver technology faster into the fabs, which means we also will bring technology to market faster.”

This is largely an ecosystem play, and in the case of the Common Platform members it combines extensive research capabilities from all three companies. “What we are able to do now is quickly ramp up our wafer knowledge,” said Mike Noonen, executive vice president at GlobalFoundries. “ That’s all a function of how fast we can move a wafer through.”

Ecosystem reverberations
Still, the decision isn’t entirely up to the foundries. No one company is big enough to do everything anymore—not even IBM or Samsung. The delay in bringing EUV to the market is a case in point. While the market has been more than ready—there’s even a building ready at the Albany Nanocenter, which IBM’s Cadigan promised the state of New York would be in use by now—the power source is still not commercially viable. It was supposed to have been ready at 45nm, and its absence is being felt acutely at 20nm because the alternative is double patterning of critical layers. By the time the 14nm back-end of line process shows up next year, multi-patterning will become the norm with double patterning on most other layers.

All of this has put a heavy burden on EDA tools and third-party IP vendors, which have to place bets in order to properly funnel R&D dollars. While it’s important to be at the bleeding edge of the market with tools and IP, because that allows them to mature along with the processes, it’s also important to strengthen offerings at 40nm and 28nm. The result is that EDA vendors hear complaints about not doing enough on either side.

“The tools we have today can do the job, but there are more issues and companies need to keep working closely together to deal with them,” said Juan Rey, senior engineering director for Mentor Graphics’ Design to Silicon Division. “When there is a need on the semiconductor manufacturing side to move at a certain pace, they generally keep in mind what has to happen on the EDA side. But the whole infrastructure has to be ready, so there may be a longer future at 10nm and beyond.”

Put in perspective, the acceleration of Moore’s Law in the short term may be an aberration, with fluctuations in the exact timing more likely to occur as design and manufacturing become more complex. He’s not alone in that assessment.

“We believe that at some point the process nodes will slow down,” said Chi-Ping Hsu, senior vice president for R&D in the Silicon Realization Group at Cadence. “Whoever has the best technology to address that last node will win in the marketplace.”

Still, understanding what that node is, and how other approaches will fit in and affect the whole design to process flow, is not clear. Billions of dollars have been spent already to bring EUV to market, with billions more being poured into the effort. It still isn’t ready, and companies are beginning to look at alternatives such as directed self-assembly just in case it never reaches commercial viability.

Moreover, the move to stacked die, which is expected to begin this year with 2.5D packaging approaches and within a couple of years for full 3D stacks with through-silicon vias, could allow things like analog, I/O and memory IP to stay at older process nodes. That, in turn, would greatly simplify the design and manufacturing digital platforms at newer process nodes, but it would render Moore’s Law meaningless for big portions of an SoC.

“2.5D and 3D are becoming active considerations in regard to what to put in the package,” said GlobalFoundries’ Noonen.

Scheduling conflicts
Unlike in the past, where there typically was one big problem to solve at each new process node (130nm was the exception because there were three—the introduction of copper interconnects, low-k dielectrics and 300mm wafers), there are more big issues surfacing at each new process node. And while things have accelerated in the short term, that’s unlikely to happen beyond 10nm.

KH Kim, executive vice president of the foundry business at Samsung Electronics, pointed to three main challenges at future nodes: process variation and parasitics, channel width and drive current choices, and modeling and extraction. Any one of these three areas can become more problematic at future nodes, Kim said.

And on the design side, things like routing congestion, fill, complex 3D modeling and verification of all types—including detailing of physical effects such as heat, electrostatic discharge and electromigration—already are difficult. At some point they will become significantly more expensive to resolve, raising questions about the return on investment for EDA and IP companies. The result may be that the entire ecosystem cannot afford to move forward to the next node at the same time.

As Gary Patton, vice president of the Semiconductor Research and Development Center at IBM, observed: “People are used to getting 50% performance and a 10% to 15% cost improvement as they move from one node to the next. In the future it will be less than 50% performance improvement with the same 10% to 15% cost benefit. It won’t be as large as in the past.”

And for most players in the design to manufacturing ecosystem, that benefit will vary depending upon their individual slice of the flow, which could further increase the gaps between players as time goes on.