Achieving Lower Power, Better Performance, And Optimized Wire Length In Advanced SoC Designs

In system-on-chip (SoC) design, wire length refers to the total physical distance of interconnects within a network-on-chip (NoC). It is a critical parameter that influences performance, power consumption, and manufacturing costs. Today’s SoCs incorporate numerous IP blocks connected by multiple complex NoCs and require efficient management of wire lengths. Excessive wire length increases latency, elevates power usage, and complicates layout in advanced deep submicron processes where interconnects dominate design constraints. Arteris’ FlexGen smart NoC IP is designed to tackle this challenge by automating NoC generation to minimize wire length while maintaining stringent performance objectives.

Manual design approaches applied to some NoC components struggle to optimize wire length as SoC complexity increases. For instance, an automotive ADAS chip design developed manually by an expert resulted in a total wire length of 313,000 millimeters. Using FlexGen without limits of performance specifications, this figure dropped dramatically to 116,000 millimeters. When performance objectives, such as bandwidth and latency requirements, were applied, FlexGen achieved 280,800 millimeters. As shown in the visual, these results underscore FlexGen’s capability to revolutionize NoC design, providing a measurable edge over traditional methodologies and optimized SoC designs overall.

Wire length optimization leveraging FlexGen, smart NoC IP. (Source: Arteris)

Wire length optimization

Wire length directly impacts design metrics, particularly for design processes where interconnects overshadow gates in power and latency budgets. Moving from FlexNoC 5 to FlexGen in an SSD controller design reduced wire length by 25%, boosting power efficiency and speeding up signal transmission. In an AI chip design, FlexGen achieved a 46% wire length reduction, a 13% decrease in total chip area, and a 10% latency improvement. While all use cases can vary based on the parameters set, typical results are expected to be around 30% wire length savings. These improvements resulted from optimized paths within the NoC’s request and response networks, which serve as the data networks. These gains also include control networks that manage service and observability, ensuring efficient communication across IP blocks.

FlexGen leverages sophisticated automation to explore NoC topologies such as tree and mesh configurations far faster than manual approaches. An SSD controller NoC required 33 hours, including manual topology editing and auto pipeline insertion, whereas FlexGen’s automation completed the task in 5.5 hours with a 25% shorter wire length. This efficiency stems from its ability to navigate white space between IP blocks while respecting blockages. These are regions where routing is prohibited to avoid shorting metal in IP blocks, ensuring optimized paths from socket locations to targets based on connectivity maps and performance specifications. Across different applications, FlexGen consistently delivers an average 30% wire length reduction, translating to power efficiency, area savings, and faster signal transmission.

Precision and flexibility

By dynamically adapting to various bit-widths, FlexGen removes rigid design constraints, making it easier to optimize NoC layouts, such as 8-bit I/O links to 2048-bit data pipes for high-bandwidth memory (HBM). Unlike rigid solutions requiring uniform widths, FlexGen supports diverse connectivity within a single NoC. Repeatable outputs within 4% for timing closure allow iterative refinement, distinguishing FlexGen from less predictable alternatives.

FlexGen’s flexibility empowers engineers to define traffic classes, including bandwidth-sensitive, latency-sensitive, and best-effort. This ensures wire length aligns with specific design goals. In a mid-range ADAS chip, this approach yielded a 35% wire length reduction and a 9% area savings compared to manual efforts. Expert users of Arteris tools at a leading semiconductor company report 15-20% wire length improvements. The tool integrates floor plan data via TCL or LEF/DEF formats and outputs to physical synthesis, delivering timing closure estimates, FIFO buffers for storage, and repeater pipelines to meet latency targets.

FlexGen, smart NoC IP enables customizable automation. (Source: Arteris)

FlexGen builds on Arteris’ extensive NoC expertise, offering a production-ready solution that significantly improves NoC design efficiency and reduces wire length compared to traditional manual efforts. Semiconductor companies achieved reduced wire length, thereby cutting power, latency, and manufacturing costs while accelerating design cycles. Whether optimizing an initiator network interface unit to a target or refining a complex SoC layout, FlexGen establishes a new benchmark for NoC design, reinforcing Arteris’ leadership in interconnect IP technology. To learn more about smart NoC IP, download the tech paper here and check out my conversation with Ed Sperling.