Addressing IC Hyperconvergence Design Challenges

Recently in an article titled “A Renaissance for Semiconductors,” my colleague Michael Sanie highlighted some of the trends that are driving next-generation product development. He detailed how designs targeting new applications are innovating through a combination of advanced process node technologies and heterogeneous integration of stacked die/3D/2.5D systems. Additionally, advanced vertically integrated toolsets and improved methodologies are tailored to customer-specific environments. This becomes increasingly necessary for computing and communication infrastructure to leapfrog and meet the demands that are now accelerated by the COVID-19 pandemic.

This evolution from chips with discrete functions combined on PCB to a 3D IC system that Michael alluded to happened in a few distinct steps. The SoC itself became increasingly complex. The use of advanced processing technologies to design the ‘digital’ part of the SoC was part of this. The use of larger and faster-embedded memories and complex I/O circuits with 100+ Gb data rates on the same piece of silicon to communicate both with the DRAM stack and analog front-end devices also contributed. Today, the SoC often integrates analog functions within the same piece of silicon, blurring the boundaries between analog and digital.

The complexity and cost of developing these systems and the associated SoC, memory sub-system, and chiplets requires a strong collaboration between design teams and EDA tool providers to enable workflows targeted for Power-Performance-Area-Cost (PPAC) convergence. This is especially important as the gap between desired versus achieved PPAC continues to widen.

These system-in-package devices present many design challenges as a result of the extreme, or hyper-converged nature of the technology they contain. From a scale complexity point of view, advanced process nodes present increased parasitics, process variability, speed, accuracy and reduced margins – all of these impacting the overall simulation time-to-results, quality of results (QoR) and cost-to-results.

As discussed, these devices contain a mix of analog and digital elements that need to be analyzed and verified as a complete system, not as separate components. This systemic complexity demands a unified workflow that can model and analyze all aspects of the design together, as one system.

IC hyperconvergence is driving innovation in many markets, from the data center to the edge to IoT. To effectively compete in these fast-growing and highly competitive markets requires first-time success for these hyper converged designs. Design costs and time-to-market imperatives simply won’t support multiple turns. To get it right the first time requires a holistic approach that supports multiple levels of analysis and verification detail. It is only through an approach like this that the substantial design risks associated with hyper converged designs can be mitigated. Attempting to “stitch together” such an environment from existing tools and flows will not work. Excessive data conversion times and loss of accuracy from these conversions are two substantial issues. The need to perform multiple design iterations creates a massive support burden that will rapidly become untenable.

According to the market research firm International Business Strategies, the cost of design verification has increased over five times between the 16nm and 5nm nodes. The need for heterogeneous analysis of multiple process technologies further increases this cost. The only way to manage these costs and compete in these new markets is with a new and fully unified approach to analysis and verification of hyper-converged designs.

To re-cap, IC hyperconvergence has created the need to analyze systems consisting of analog and digital components as one system, with the need for enhanced speed and accuracy. A fully integrated mixed-mode circuit simulation capability is needed that can seamlessly address all the required analysis modes and present the results in a unified design environment.

Early adopters and drivers for hyper-converged system-in-package designs include:

• Mobile and consumer, including handsets, wearables, Wi-Fi routers and IoT, with 5G and sensors
• Telecom and infrastructure, including 5G base stations and servers
• Automotive and transportation, with ADAS and infotainment applications
• Medical, industrial, defense and aerospace

There is a call in the industry for new, highly integrated design tools and flows to address the demands of IC hyperconvergence. These requirements set a high bar for integrated tools and designs flows to facilitate a new level of holistic analysis. The EDA landscape will need to change to address these important requirements.