How to deal with a variety of issues that can cause premature aging in circuits.
Advanced, short-geometry CMOS processes are subject to aging that causes major reliability issues that degrade the performance of integrated circuits (ICs) over time. Degradation effects causing aging are hot carrier injection (HCI) and negative bias temperature instability (NBTI), in addition to positive bias temperature instability (PBTI) and time-dependent dielectric breakdown (TDDB). Below 90 nm, consideration of these effects is becoming mandatory for design flows targeting quality and reliability. This paper describes the state-of-the-art simulation flow that can help designers address these issues and to create more reliable designs.
These particular reliability effects modify the fundamental behavior of the transistors, such as threshold voltage (Vth) and the mobility factor [1]. No applications that make full use of the process performance are truly safe. These changes will affect timing delays, drive currents, leakage, linearity, and every possible specification that may appear in IC design, be it for automotive, biomedical, military-aerospace, wireless communications, or video. Basically, all industry sectors are potentially affected.
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