Addressing Silicon Lifecycle Scaling Demands

In today’s competitive business landscape, navigating complexity can be a decisive advantage, but it also presents significant challenges. Three crucial trends driving the rise of complexity are technology scaling, design scaling and system scaling. Traditionally, Design for Test (DFT) solutions have focused on the die level; however, these challenges present opportunities at the package and system levels. To effectively meet customer needs, Siemens EDA has taken proactive steps to tackle the challenges they encounter. By utilizing innovative Silicon Lifecycle Management (SLM) solutions, they successfully deploy advanced systems at scale, enabling clients to thrive in a competitive market.

Fig. 1: Three scaling challenges that affect semiconductor makers. Semiconductor companies can leverage data from verification and validation phases to create a true digital twin of their chips and systems. This approach opens new possibilities for gaining data-driven insights into performance, reliability, safety and security.

Siemens EDA’s unified approach throughout the lifecycle of chips and systems empowers new applications and visibility. Its SLM strategy helps semiconductor companies fully leverage the competitive advantages of complexity without compromising performance. SLM solutions provide a comprehensive infrastructure that significantly enhances design testability, providing superior testing quality while uncovering defects and hidden yield limiters. By seamlessly transitioning from testing to system debug and validation, these solutions ensure a robust end-product. Moreover, they integrate all these capabilities for continuous in-life monitoring, delivering unmatched reliability and performance.

The bottom-line benefits of such a holistic SLM approach are substantial. The IC design and production process becomes more responsive, agile and cost-efficient. Devices become easier to integrate into end products, and after deployment, are more reliable and more secure. The ability to monitor what matters throughout the device’s life enables preventive maintenance and continuous performance optimization in the field.

Fig. 2: A silicon lifecycle management flow.

SLM is a key element of Siemens’ strategy to use a digital twin to address complex challenges and drive innovation effectively. A digital twin of a product is a virtual representation of the actual product. It allows the product to be designed and verified in a virtual environment before the physical version is created.

Digital transformation is an ongoing journey, even for companies that have been digital for decades. Siemens’ software and the comprehensive digital twin enable companies to optimize their design, engineering and manufacturing processes.

Automation crucial to technology scaling

SLM solutions are inherently multi-domain, making it crucial to adopt best practices for DFT, yield analytics and functional monitoring activities. SLM facilitates the seamless collection of data from chips after they are deployed in the field, paired with a powerful suite of tools for data analysis and interpretation. This combination not only provides essential insights into system performance but also empowers organizations to enhance reliability and drive innovation.

Technology and system complexity drive the need for enhanced fault modeling and detection, particularly for more recent types of faults, such as System Design Errors (SDEs) and Static Data Corruption (SDCs) [1]. These faults not only depend on transistor-level effects but also system-level conditions, including latent defects, aging and the impact of software workloads on power delivery. Consequently, detecting failures during manufacturing and within end products has become critically important. If companies do not upgrade to advanced DFT tools and methodologies, systems-on-chip (SoCs) designed at advanced technology nodes may struggle to meet the high-quality standards demanded by today’s market.

Automation, especially when it can adapt and optimize in real-time, is a critical aspect of the design process. The primary goal of technology scaling is to achieve precision and fidelity in automation, which drives innovation and enhances efficiency. By employing defect-oriented testing and cell-aware diagnosis capabilities available in Tessent Diagnosis, we can achieve the accuracy required to effectively model, detect and diagnose physical defects. However, this enhanced capability for defect identification also complicates the pattern generation process, necessitating the creation of additional test patterns.

Packetized scan delivery for design scaling

Difficulties with transistors in a design stem from the increasing complexity of designs, particularly in terms of size and the costs associated with DFT implementation. This complexity leads to more parallel work on cores and blocks, as well as an increase in duplicate core usage. A common approach is to complete the physical design at the block level and then abut these blocks together, which is known as a tile-based design flow. However, this trend complicates the traditional DFT implementation process.

Hierarchical DFT flows have been effective for many years, enabling DFT to be integrated and patterns to be generated at the block or core level. These can then be mapped to the top level. Unfortunately, the rising number of identical cores and the use of tile-based flows, which lack top-level logic, make even hierarchical flows more challenging. These challenges include planning efforts, tiled designs with abutment, test costs, routing and timing closure.

Packetized scan delivery addresses many challenges associated with scan distribution in complex SoCs. This approach allows for the simultaneous testing of multiple cores while utilizing only a few chip-level pins. It can efficiently test any number of identical core instances in nearly constant time, thereby reducing the need for padding even when cores have differing pattern counts or scan chain lengths.

Siemens EDA’s Tessent TestKompress and Streaming Scan Network (SSN) solutions provide packetized scan delivery. Designed to address common DFT challenges in testing SoC designs, these systems separate core DFT optimization from integration into the design, providing available input/output interfaces. This method effectively decouples test delivery from core-level DFT requirements. For instance, in core-level compression, the configuration can be defined entirely based on the chip I/O limitations. Decisions regarding which cores will be tested concurrently are made programmatically, rather than being hard-wired as in traditional pin-multiplexed approaches.

Fig. 3: Packetized scan delivery architecture.

An additional advantage of packetized scan delivery is its adaptive intelligence. The specific cores to be tested can be selected after the DFT design is finalized and the test patterns have been generated. Once the user identifies the cores for testing, the packet delivery process is optimized to ensure the most efficient delivery possible.

System scaling

The third trend driving complexity is system scaling. As technology and designs scale, more and more functionalities can be implemented in a single integrated circuit (IC), and more ICs can be integrated together in a single package.

Multiple challenges result from system scaling, for example:

• optimizing the system architecture before tape-out
• ensuring functional subsystems work together correctly in silicon
• meeting the functional spec
• managing the utilization of shared resources
• optimizing software for the specific hardware implementation

Integrating multiple chips into a single product becomes significantly more complex, especially when using 3D integration techniques that combine several chiplets into a system-in-package. A comprehensive set of hardware-based functional monitoring tools, provided as silicon IP, can help manage this complexity. Functional monitoring should offer a complete overview of the chip, along with detailed insights into each IC subsystem. It must also enable system-level visibility of both hardware and software, enhancing the information provided by DFT structures. Additionally, it should deliver an accurate and cohesive picture right from the moment the system boots up.

Functional monitoring also needs to provide data filtering and collection according to:

• configurable criteria
• the flexibility to choose which subsystems are of interest
• data pre-filtering inside the IC
• timestamps
• programmable cross-triggering for data correlating collection across different subsystems
• off-chip data transfer mechanisms compatible with the system’s functional interfaces
• tools to build and integrate analytics applications that consume the collected data

To maximize the effectiveness of functional monitoring, it is essential to have the flexibility to analyze and respond to insights from both distributed systems (on-chip) and centralized resources (off-chip), whether in real-time or after additional processing. It is important to minimize the resources and overhead needed for integration into the chip design. These capabilities facilitate data collection and insight generation, leading to a higher return on investment.

Fig. 4: Tessent Embedded Analytics functional monitoring solution.

Functional monitoring, provided by Tessent Embedded Analytics, and the insights generated by data collection offer a unique form of adaptive intelligence. In this case, it provides an opportunity to optimize functional operation and improve the end-product application.

Deploying at scale

Many issues encountered during the development phase also arise after the IC or embedded system has been deployed. For instance, structural tests are necessary to detect aging-related reliability problems or silent data errors (SDEs). Some issues only become apparent after deployment; low-probability, high-impact performance problems may manifest under real-life software loads. These issues must be detected, prioritized, investigated and resolved like any other bugs.

One of the biggest challenges in scaling systems is the aging of silicon and the inherent reliability issues that arise from it. By analyzing data from DFT structures throughout a product’s lifecycle and combining it with similar data collected during pre-deployment phases, we can identify field failures and develop a model for aging and reliability. This approach enables us to predict potential failures in advance. A key application of this methodology is the detection of SDEs caused by data corruption.

Deterministic in-system tests are already in use and are expected to grow in adoption. They can be instrumental in handling the aggressive growth of test data volumes. Tessent In-System Test enables the creation of high-quality, deterministic test patterns. Tessent In-System Test (IST) complements Tessent SSN, enhancing its ability to be used in an in-system, in-field environment. Designers can apply embedded deterministic test (EDT) patterns generated using Tessent SSN software directly through the SSN bus, using the in-system test controller.

Fig. 5: In-system deterministic test logic.

Within any SLM solution, continuous testing and monitoring of devices are required to ensure optimal performance, reliability and safety throughout their operation. Tessent In-System Test enables the application of high-quality, deterministic test patterns for in-system and in-field testing throughout a chip’s lifecycle.

In summary

Every challenge presents an opportunity. Silicon lifecycle solutions offer significant advantages for companies that capitalize on trends in technology, design and system scaling, particularly those deploying at large scales. Silicon Lifecycle Management involves the seamless collection of data from chips after they have been deployed in the field. This process includes a suite of tools that effectively consume and analyze the data, providing critical insights into system performance.

Beyond the silicon-level infrastructure, end-to-end SLM requires a shift from traditional chip design tooling workflows. It demands the implementation of a comprehensive closed-loop digital twin concept, which facilitates the transfer of data from live, in-field products back for analysis and evaluation. This data can be correlated with earlier stages of design, development, simulation, manufacturing and testing.

As the pace of innovation continues to produce more digital systems each year, we generate exponentially more data that can be analyzed and potentially monetized. This makes digital transformation an ongoing journey, even for companies that have been digital for decades.

The complexities of modern systems can be addressed by integrating foundational elements that tackle various scaling challenges with cutting-edge technologies. Most importantly, the substantial benefits of adopting SLM solutions are most easily realized when these foundational elements work together seamlessly.

Tessent Silicon Lifecycle Solutions from Siemens EDA accelerate time to market by simplifying design complexity through the use of high-quality DFT. These solutions include advanced debugging, safety and security features, as well as in-life data analytics to address the evolving challenges of today’s silicon lifecycle. To learn more about Tessent SLM, please visit www.siemens.com/tessent.

Reference

1. Hyperscalers lengthen server lifespans to save billions – Interface