Addressing Three Big Challenges In Silicon Realization

There is no better way to gain insight into prevailing technical challenges than bringing together industry experts to share experiences and proposed solutions. Silicon realization—the ability to design and build today’s complex semiconductors—is one domain with no shortage of challenges. The quest for the best power, performance, and area, and delivery of first-time-right silicon, requires innovative solutions for designing and verifying complex chips.

Just a few weeks ago, Synopsys sponsored the Silicon Realization TechSummit to present and discuss the challenges in three key areas of chip development:

• The Move to Multi-Die: unified and holistic solutions to integrate disparate process technologies to drive beyond-Moore enablement
• Energy Efficient Design: meeting performance goals while keeping energy consumption under control in environments thermally constrained or requiring extended battery life
• Reliability, Resiliency, Security: robust design and verification practices, scenario testing, and adherence to standards

Each of these three topics was covered in depth with an introductory presentation followed by a panel of thought leaders from chip suppliers, system developers, and academia. The first segment was opened by Shekhar Kapoor from Synopsys, who said that multi-die technology is the next major advance in semiconductor design productivity. He cited a published example of a system-on-chip (SoC) design that cut chip manufacturing cost nearly in half by moving from a single die to heterogeneous 3D-stacked implementation using hybrid bonding technologies to interconnect the dies.

Kapoor stressed that successful multi-die design requires innovation in many electronic design automation (EDA) tools, linked into a holistic, system-level flow. He concluded by discussing the solutions available from Synopsys to architect, design, verify, validate, build, and test 2.5D/3D chips efficiently and successfully.

This talk was followed by the panel “An Industry Perspective on the Coming of Age of Multi-die Design” with participants from Broadcom, Deca Technologies, Intel, Samsung, and Ventana Micro. Four themes emerged from the panelists:

• Lack of scaling, memory bandwidth, and lower costs are pushing designers to multi-die chiplets
• Multi-die design supports both single-die disaggregation and multi-package integration
• Unified silicon, package, and system co-design and co-optimization are needed to speed path to optimal design
• Collaboration across the ecosystem and availability of common standards are essential to accelerate multi-die success

Synopsys’ Solaiman Rahim began the energy efficient design segment by saying that there is “no more free lunch” in power reduction from design scaling and Moore’s Law. He presented a thought-provoking graph showing that, at the current trend, compute energy demand will equal world energy production in 30 years.  With electricity grids already nearing capacity, this will overload the system unless there is a massive reduction in power consumption.

The chip industry can contribute substantially with energy efficient design, but Dr. Rahim noted some of the factors that make this challenging. He argued that the industry needs a “shift-left” in power analysis and optimization. This enables power exploration at both the architectural and micro-architectural stages, efficient implementation of low-power design techniques, and accurate power signoff. He also discussed how the Synopsys software-driven solution for energy efficient design provides these capabilities.

The provocative title of the next panel was “1000X Improvement in Energy Efficiency: What’s a chip got to do with it?” Experts from Datapelago, Intel, NVIDIA, SiFive, and Synopsys offered their perspectives, which ranged from the ubiquity of artificial intelligence (AI) applications to how edge/cloud tradeoffs affect power.

Much of the discussion centered around complementing the shift-left mentioned in the presentation with a “shift-right” that delays power decisions until runtime when possible. Dynamic voltage and frequency scaling (DVFS), silicon lifestyle management (SLM) on-chip monitors, and the challenges of determining representative workloads for “software that hasn’t been written yet” were all cited as reasons for adjusting power dynamically in real time.

“Reliable and Secure Silicon Throughout the Lifecycle” by Adam Cron of Synopsys introduced the key issues for the final portion of the forum. He surveyed some ways to detect and, when possible, correct random hardware failures. These range from traditional methods such as parity bits and memory error detection and correction schemes to automated triple modular redundancy (TMR) insertion of critical safety registers.

Cron picked up on the shift-right concept by discussing the vital role played by SLM solutions such as PVT and path margin monitor (PMM) IPs embedded in the silicon. These IPs enable SLM analytics to spot aging effects and other weaknesses in chips before in-field failures occur. They can also be used to catch anomalous behavior possibly due to a Trojan Horse activation or other security breach. He presented the Synopsys SLM solution and showed how it tied into the implementation flow for maximum impact.

Many of the same themes were carried forward in a panel featuring thought leaders from Arm, Microsoft, NXP, and Stanford University. It was clear from the position statements that the problem has many dimensions: reliability, resiliency, security, safety, dependability, availability, and serviceability. Panelists noted that PMMs enable continuous chip test in the field in mission mode, reflecting real-time conditions and supplementing traditional manufacturing tests. They also made an interesting loop back to the start of the forum, pointing out that multi-die disaggregation may open or expose security attack points at the connections between the dies.

The three sessions all proved expansive in breadth, with deep dives into several key topics. There is much more information than can be summarized in a single blog post. Fortunately, recordings of both the talks and the complete panel sessions are available to watch on demand. Interested readers are invited to hear much more on reliability, resiliency, and security, energy efficient design, and the move to multi-die.