Advanced 3D Design Technology Co-Optimization For Manufacturability

By Yu De Chen, Jacky Huang, Dalong Zhao, Jiangjiang (Jimmy) Gu, and Joseph Ervin

Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. It is a continuous challenge to meet targets of both yield and cost, due to new device structures and the increasing complexity of process innovations introduced to achieve improved product performance at each technology node. Design for manufacturability (DFM) and design technology co-optimization (DTCO) are widely used to ensure successful delivery of both new processes and products in semiconductor manufacturing. In this paper, we develop a new 3D DTCO model which combines 3D structure optimization and electrical analysis. We discuss how this 3D DTCO model can be used to improve product yield and accelerate product delivery timelines in semiconductor manufacturing.

1. Introduction
The importance of DTCO in almost every semiconductor design and manufacturing process can hardly be overemphasized. In conventional semiconductor design, numerous techniques are used to improve lithographic resolution, such as optical proximity correction (OPC) and phase shifting mask (PSM). Designs are generally signed off for manufacturing after two dimensional, single-level checks (2D design rule checks or 2D DRC) are completed.

This design process worked quite well until more complex, multiple patterning processes were introduced over the last few years. The complexity of deposition and etching in these new lithography processes have now made it virtually impossible to separate process steps from the design, and the variability in these complex processes brings further design challenges. In addition, certain types of mistakes in design and layout are not obviously visible in two dimensional DRC, making it difficult to fully verify manufacturability and device performance. Therefore, traditional 2D DRC is no longer sufficient. A more precise 3D DTCO model containing process variation analysis and device modeling is now required when new and more complex patterning processes are used.

2. Modeling Flow
Figure 1 shows an advanced 3D DTCO modeling process, developed in Coventor’s SEMulator3D virtual fabrication platform [1].

Fig. 1: 3D DTCO modeling process, developed in 
Coventor’s SEMulator3D virtual fabrication platform.

After inputting 2D layout information and performing 2D DRC checks, process and variation information are added into the design flow to build a highly-accurate 3D model in SEMulator3D.  The 3D model can be used to search and verify problem areas or hotspots, which may have been highlighted during 2D DRC. Although some hotspots can be identified using simple 2D DRC, these results may not be complete, due to process variability in deposition, etch, or other lithography processes that are not reflected in 2D DRC. 3D process modeling includes process and structure information, and can highlight structural issues such as minimum insulating distance, contact area, or other yield-limiting design problems.

Key process parameters can also be easily identified through 3D DTCO modeling. Process parameters and designs can be evaluated with respect to certain critical targets such as CDs, yield limiting spacing, 3D design rule violations, resistance/capacitance, and other process and design issues. Using these screening results, process engineers can concentrate their efforts on controlling critical process results by designing inline measurement and metrology specifications. Alternatively, they can focus on process controls that will reduce variation in critical process steps.

Once the process window is confirmed in SEMulator3D, a user can extract electrical characteristics of a transistor and explore the effect of process variability on device operation. Device performance can be measured across changes in patterning, lithography, etch, deposition, and other process integration effects.

In this study, we implemented a typical FinFET process flow in SEMulator3D, where the patterning flows were based upon 14nm finFET technology. After 2D DRC and 3D DTC checks, we determined which process parameter(s) had the most significant impact on the fin top CD, and analyzed the impacts of these parameters on device performance.

3. Results

3.1 3D Hot Spot Checks
Figure 2 shows an example of metal connections in Back End of Line (BEOL) development along with some highlighted hotspots. The location of each region in the device is identified in a coordinate structure, with blue marks representing possible failure points identified on the 3D virtual model during DTC checks of the minimum gap, minimum contact area, and minimum metal width detection.

Fig. 2: Example of metal connections in Back End of Line (BEOL) development, and highlighted hotspots.

Using this DTCO process, designers and process engineers can quickly optimize both their designs and processes by performing “virtual” fabrication and avoiding lengthy fab-based learning cycles.

3.2 Analytics
We subsequently identified the most important process parameters that modulate fin top CD using a “Definitive Screening Design (DSD)” [2] algorithm, which is suitable for exploring a wide parameter space. Film thickness, fin spacer thickness, mandrel etch depth, and several other metrology parameters were defined as targets in this simulation. The screening design flow allows many process parameters to be included in the study, so that we can have the confidence to accurately identify factors that affect our process (Figure 3).

Fig. 3 – Analytics input showing process parameters included in the DSD study.

Regression results identified 5 significant parameters in 20 simulation runs. The most significant parameter was the thickness of the spacer oxide deposition, while the second most important was pad nitride deposition. The regression model demonstrated a high confidence level (r2 = 0.98) at the end of 20 simulation runs (Figure 4).

Fig. 4: Regression results from the DSD study

We then varied spacer oxide thickness to attempt to control the Fin Top CD. In this example, we showed that the maximum spacer oxide thickness was 31nm, since the RIE etch process failed at an oxide thickness of 32nm. The process margin for spacer oxide thickness in the SADP process was -2nm to +3nm. The limitation of spacer oxide and the corresponding fin top CD are summarized in Figure 5.

Fig. 5: Results showing the limitation of the spacer oxide and the corresponding fin top CD.

3.3 Electrical analysis
In our electrical analysis, we performed a device simulation based upon the classic drift-diffusion model. We generated transistor IV curves and performed automatic device parameter extraction from those curves (Figures 6 and 7). This step provided insight into how process integration decisions, such as film thickness and allowed unit process variations, impact transistor device performance.

Fig.6: NMOS & PMOS Ion-Ioff from the device simulation.

Fig. 7: Ieff/Vt/DIBL from the device simulation.

4. Summary
In this paper, we have discussed a 3D DTCO modeling flow, in which DSD screening and electrical analysis are used to predict the impact of process parameters on device performance for a 3D FinFET model. As semiconductor technology advances, 3D DTCO flow is becoming more valuable in improving yield by minimizing systematic, random and parametric defects, primarily through the prevention, detection, and repair of projected hotspots. Design process technology co-optimization (DTCO) for manufacturability will be a key success factor for companies that wish to succeed in achieving on-time delivery of new semiconductor products.

References
[1] http://www.coventor.com/products/semulator3d
[2] L. Xiao, et al., “Constructing Definitive Screening Designs Using Conference Matrices”, Journal of Quality Technology, Vol. 44, No. 1, January 2012