Advanced Defect Inspection Techniques For nFET And pFET Defectivity At 7nm Gate Poly Removal Process

By Ian Tolle, GlobalFoundries, and Michael Daino, KLA-Tencor

During 7nm gate poly removal process, polysilicon is removed exposing both NFET and PFET fins in preparation for high-k gate oxide. If the polysilicon etch is too aggressive or the source and drain are not sufficiently protected, the etch can damage the active region and render the FET inoperative. Different materials are used in the active region for NFET and PFET that have different susceptibility to the polysilicon etch. To sufficiently monitor this defect, we must have good detection of damaged active regions on both PFET and NFET. However, PFET and NFET regions have very different optical noise characteristics due to varying levels of process uniformity. In addition, the distance between NFET and PFET has continued to shrink with the design rule, making evaluating each independently with optical inspection tools increasingly difficult. In this paper, we introduce new techniques to independently monitor both NFET and PFET defectivity, with improved performance over current methods.

I. INTRODUCTION
The gate last high-k metal gate integration scheme introduces several defect types that need to be monitored, of which generally agreed as the most important are etched out fins [1]. In gate last processing, a sacrificial material is used for the gates while the source and drains are being fully processed. Once the source and drain are completed, the sacrificial material (Polysilicon) needs to be removed to make way for the high-k gate oxide and the metal gate stack. In order to only remove the sacrificial gate and leave the source and drain unaffected, the source and drain are protected by an oxide in the z-direction and gate spacer material in the plane of the wafer. If there are any weak points in the spacer or oxide interface, the source and/or drain can be eroded during this process. When this erosion becomes so severe that the entire source/drain is destroyed rendering that finFET inoperative, the defect is referred to as an RX hole. Optimizing the process conditions to minimize and/or eliminate RX hole defects on both PFET and NFET fins is a requirement for all gate last FinFET technologies. In this work we report on the challenges and solutions in developing a robust inline inspection and review strategy for these defect types at the 7nm technology node.

II. RX HOLE MONITOR CHALLENGES FOR 7NM FINFETS

A. Inspection
To adequately monitor RX holes, the inspection platform must be able to consistently detect them on both PFET and NFET. It also beneficial during process development to report the P and N defect count independently, to gauge the effect of different process conditions. The inspection system must also be tolerant of the large process variation that is intrinsic of technology development. Broadband plasma (BBP) systems can meet these needs to a varying degree dependent on the particular model. In this paper we will discuss the results and limitations of 29xx BBP systems to monitor RX holes for 7nm technology development.

B. SEM Review
Scanning electron microscope (SEM) review of optically detected defects is critical to identify the particular defect type. RX holes are defects that reside under a thick layer of oxide at the monitoring step of poly gate removal which presents a significant challenge to be able to obtain an electron image of the defect. In addition, the xy dimensions are closer together and the aspect ratio of the gate is higher than previous technology nodes, creating new challenges for SEM review tools. We will also discuss the SEM review solutions used in this study.

III. METHODOLOGY

A. Broadband Plasma Inspection
The introduction of 29xx BBP inspection systems brought several improvements to hardware and software to provide state-of-art inspection solutions for advanced technology nodes [2]. In this work we developed custom Boolean design layers using EDA software and then included these layers as part of the inspection recipe, to improve detection and binning of NFET and PFET RX holes. Fig. 1 shows an SRAM array example of a pRX hole patch alongside the associated custom design clip, while Fig. 2 shows a logic defect example of a pRX hole. The design clip has been specifically made for clear PFET (blue) and NFET (red) fins identification. Note from the array patch the dark and bright horizontal lines are PFET and NFET regions, respectively. Although is it fairly easy for the human eye to identify PFET vs. NFET in SRAM from the repeating pattern alone, this is not possible in logic regions, as shown in Fig. 2, where the design layout can be highly variable. For these logic defects, assigning the defect to either the N or P bin is accomplished by comparing the defect location on the wafer to the corresponding location in the design and calculating the density of PFIN or NFIN custom layer within the defect’s Extended Bounding Box (EBB) shown as the red dotted box on Fig. 2b.

Fig. 1 Shows a pRX hole patch image in (a) and the associated custom design clip in (b) in SRAM array. Note in the patch image (a) how the bright and dark lines correlate to NFET and PFET fins in (b), respectively.

Fig. 2 Shows a pRX hole patch image in (a) and the associated custom design clip in (b), in logic. Here in the patch image, the bright and dark lines correspond to either fin or STI. Note that the patch and design clip are not to scale.

However, for array defects, the EBB is too large to accurately assign the defect to either P or N, since the pitch is much tighter. Therefore, a new feature in the inspection recipe was leveraged in this study, referred to as super•cell™. This feature allows for separation within the SRAM array to independently inspect PFET and NFET, providing optimized detection for each device type. It can also be used for binning, to determine the population of NFET vs. PFET RX holes. Fig. 3 shows the patch image (a) and super•cell performance (b) for a NFET RX hole (nRX hole). The patch image shows a clear optical difference between NFET (bright in the patch) and PFET (dark in the patch). The super•cell result is shown with the center of PFET highlighted with a white line transitioning to the center of NFET shown as black. Note the clear separation the algorithm achieved.

Fig. 3 Example patch image for a nRX hole in (a) with the super•cell result shown in (b). The super•cell algorithm was clearly able to separate NFET (bright) from PFET (dark). This separation is used for optimized detection of both nRX and pRX as well as providing binning to estimate the ratio of pRX to nRX holes.

B. SEM Review
In this study, higher landing energy of the latest generation SEM tools has been critical to characterize and monitor RX holes. To improve the contrast to the defect further, grayscale image has been mapped to a color scale to better highlight the defect to the human eye. Fig. 4a shows this new imaging approach to reveal a pRX hole. The color mapped SEM image shows the underlying fin structure in purple hue with the gate trenches in a red/green hue. The pRX hole can be identified by missing purple hue on the center PFET fin. To better highlight the defect, the custom design clip is overlaid with the SEM image in Fig. 4b. The defective fin is outlined in white.

Fig. 4 Shows a pRX hole high landing energy color mapped SEM image without and with customer design layers overlaid (a) and (b), respectively. The defective PFET fin is highlighted with a white border in (b).

IV. RESULTS

A. Super•cell vs. Traditional Methods
Prior to the addition of super•cell, only traditional optical attributes were available to attempt to separate PFET vs. NFET in SRAM. Using local contrast and gray level (referred to as roughness and brightness, respectively), PFET and NFET can be separated to some degree. Fig. 5a shows pRX (colored pink) and nRX (colored green) separated by red cut lines that create two bins. Note the population of SEM non-visual in the NFET bin that does not exist in the PFET bin. These nuisance events on NFET can be efficiently removed using signal attributes that are more aggressive than what is used on the PFET bin. This difference between PFET and NFET nuisance tuning can be seen shown in Fig. 5b and c. Although PFET vs. NFET binning strategy appears to work fairly well in this case, it can be very susceptible to process variation. Fig. 5 shows the result on a subsequent lot. Note the observed inverse behavior of PFET containing a large population of SEM non-visual nuisance defects as well as a pRX hole getting binned into the NFET bin. The large difference in the binning on the subsequent lot compared to the setup lot can be attributed to expected process changes, and wafer to wafer variability during development. The inspection recipe must be tolerant of such variation.

Fig. 5 NFET and PFET separation using traditional optical attributes is shown in (a). Using this separation, PFET (shown in (b)) and NFET (shown in (c)) can be tuned separately to account for the intrinsic noise on each.

Fig. 6 NFETand PFET separation performance on follow-up lot using traditional optical attributes. Note the inverse behavior compared to the setup lot showing that PFET is now noisier than NFET.

Super•cell PFET vs. NFET separation uses an algorithm that is more robust to process variation and thus does not suffer from the instability. This is illustrated in Fig. 5 and 6. When super•cell is used to separate NFET from PFET, the algorithm calculates a location metric that scores how close the defect is to NFET. This attribute is referred to as super•cell Attribute #1 and is used to create NFET and PFET bins instead of the optical attributes. The result of this new binning is in Fig. 7a. Note the pure separation of NFET vs. PFET in the ends of the plot with a narrow transition region of low confidence nRX holes. This is simpler than what was used in Fig. 5a, but the real value is the stability to process variation that cannot be achieved with traditional methods. The same subsequent lot was run on the super•cell enabled recipe and the resulting binning can be seen in Fig. 7b. Note the similar performance achieved on the subsequent lot that was achieved on the setup wafer. This type of stability is a requirement be able to evaluate process splits and not have error from an inspection tool be propagated to DOE split analysis.

Fig. 7 NFETand PFET separation performance on setup (a) and follow-up lot (b) using super•cell. Note the purity of the binning remains constant for both wafers and thus provides recipe stability required for evaluating DOE splits.

B. Results on Etch Split Lot
Three candidate etch conditions were used to evaluate this new capability for process development: POR, ammonia and hammer etches. The “hammer” etch was simply a longer POR etch and the ammonia etch uses an entirely different chemistry than POR. Using this new methodology, every reported defect can be categorized as PFET, NFET, CND (cannot decide), or STI (Shallow Trench Isolation, meaning no fins present). This detailed reporting provides additional information from the inspection tool on the etch split conditions that would otherwise be manually extracted from the limited sample of SEM review images. The relative defectivity of each defect type across the different process conditions is shown in Fig. 8, clearly showing that the POR and hammer etches have similar ratio of NFET to PFET RX holes but the ammonia etch has the opposite behavior. This analysis can help to quickly provide PFET vs. NFET feedback for process splits.

Fig. 8. Illustrates the defect count comparison across different etch conditions (POR, Hammer, Ammonia) Defects are assigned to either NFET, PFET, CND (Cannot Decide), or STI (no fins present).

V. SUMMARY OF CONTRIBUTIONS AND FINDINGS

In this paper, we reported on the new inspection recipe capability of super•cell for array defects paired with binning based on custom Boolean design layers for logic defects, providing a superior inspection solution that cannot be achieved otherwise. The inspection results were confirmed through the use of high landing energy SEM review with color mapped images and was an integral piece of this study. The new inspection results and SEM review capability provided invaluable information for process splits to debug defectivity (Fig. 8), and can be further extended as an automated in-line monitor for production.

REFERENCES
[1] A. Srivastava et al., “Non-traditional inspection strategy for inline monitoring in excursion scenarios: Defect inspection,” Proceedings of ASMC, May 2016, pp. 197-200.
[2] M. Daino et al., “Line End Voids defectivity improvement on 64 pitch Cu wire interconnects of 14 nm technology: Defect inspection,” Proceedings of ASMC, May 2016, pp. 60-64.

This paper was originally published in the proceedings of the SEMI Advanced Semiconductors Manufacturing Conference (ASMC2018), April 30 to May 3, 2018, Saratoga Springs, New York.