Advanced Nodes Drive Changing EDA Requirements

With new technical requirements of today’s bleeding edge manufacturing processes propelling the ecosystem of semiconductor foundries, EDA tool suppliers and IP developers, work is being done behind the scenes like a well-conducted orchestra to make sure customer designs can flow through a foundry when the time comes.

One of the areas in the design process where new processes are felt acutely is in the back end, after place & route.

Mary Ann White, director of product marketing for the Galaxy Design Platform at Synopsys, explained its TCAD side of the company addresses simulation of things like the 3D effects of the transistor and the modeling, where adjustments must be made for new processes.

“At the same time,” she said, “things can result from that like HSPICE simulations, for example. New BSIM CMG models had to be developed because of the finFET transistor. And now the question is — and we’re definitely taking a look at it since we’re heavily involved with UC Berkeley — what’s happening with 10nm and 7nm? Will there be more SPICE model changes that are required or was the BSIM CMG enough? That’s something that’s definitely under investigation.”

One of the earliest places that Synopsys engages with a foundry when it comes to a new process node is in the SPICE world, as well as with extraction. The extraction tool must understand what kind of different finFETs there are. “For 16nm, because of the 3D effect, [the extraction tool] needed to understand how to extract the middle end of line (MEOL) effects, the back end of line (BEOL) effects, because it is two to three times more capacitance, and finding that capacitance — the extraction tools had to be updated to be able to handle that,” White pointed out. “As we move into 10nm and 7nm, or below, there are definitely other things. Now we’re seeing there are ways of having other fins. You could have a triangle fin, or a diamond fin; those have different properties associated with them.”

Extraction also is used by the foundries to help with development of the process. A foundry will see what the extraction is like with the new process, develop the process models that then get shipped with the process, which is then what is used for characterization. Those are the SPICE models version 0.1 or SPICE models version 0.5, or TSMC will use 1.0, which means that’s the production models, she explained.

The engineering team also will use the parasitic extraction tool after place & route in conjunction with a DRC/LVS sign-off tool, which does the repair and fixing based on the design rules. White added this is another area that has to change because the design rules effectively grow bigger with each process node. “The number of rules more than doubles moving from 28nm to 20nm, and again to 14nm. You can expect that those design rules will continue to grow. That’s where we also come into the foundries and start working with them early to make sure that we’re understanding what’s happening with the rules, that the routing adheres to those rules, and the physical verification knows what the rules are. In essence, there’s a lot of background work. We like to say we’ve got almost a decade of finFET experience even though it’s really only coming to production this year because of all of these early things that you have to think about.”

“Primary” tool vendors have more influence
It’s probably no surprise to hear that foundries will have tools that they prefer to work with, and according to sources, tend to have primary vendors that they may or may not publicly state. Obviously, it behooves the foundries to be friendly with everyone, but it does beg the question as to whether it’s just a matter of resources.

Steve Carlson, group director of marketing at Cadence, observed that the amount of parallel development and collaboration has dramatically increased. “It used to be kind of a serial process: get the DRM done, throw it over the wall to EDA, then EDA tools would do their thing, then the IP guys would go. Now, it’s much more in parallel, and more information is shared.”

As to the question of whether each foundry can do this with every EDA vendor, he said that to cover the market, the foundries need to support all the major flows, but it’s a question of priority. “Being the first one on the list — a lot of things get solidified in those initial collaborations, so as the process rules get hardened, then the opportunity for the second and third EDA vendors to influence diminishes. So it’s a very advantageous position to be first in the relationship with the foundries.”

That relationship is far from static, though. “There is a give and take between what the tools can do, what the physics of the process offer, and what’s needed for a particular IP subsystem, and they all interplay together,” Carlson said. “If you can’t get 2.1GHz on this particular processor configuration then the customer isn’t likely to move, and you’ll be building a fab that doesn’t suit the needs, so there is a process on the loosening and tightening of design rules and getting that performance versus yield tradeoff. The customer does get involved earlier, as well. We have seen pressure for 10nm and lining things up for 7nm well in advance where the end customer wants to get their hands on some tool capabilities so that they can start doing their own evaluation, and we don’t even have the first version of the DRM.”

There’s also a distinct perspective from the EDA tool provider’s side. “With 10nm, there are a couple of camps,” said Synopsys’ White. “It’s either going to be triple patterning (litho-etch litho-etch) or self-aligned double patterning. The way we look at it, we have to develop for both of those techniques, and the foundries haven’t decided which. They are also under investigation — so it’s almost like double the effort versus what we did for double patterning because that one is now defined. 20nm helped with that and then it easily moved to 16 and 14nm. But now with this triple patterning, it’s what we are calling multiple patterning modeling. All the tools have to be updated.”

Mentor Graphics claims to have a unique vantage point as its Calibre Division works with the major foundries as each foundry is doing their process development. “We are the first ones in there, in particular for physical verification products like Calibre DRC,” said Michael White, director of product marketing for Calibre Physical Verification at Mentor Graphics. “They use our tools to help validate the initial test cases they are making as they are doing process development. We have to work very closely with them as they are doing that. Then, the initial test cases and so on are used to create portions of ultimately what will be the first sign-off deck for that new technology node. That sign-off deck is then used internally by the foundry for doing their own IP development and validation, and it’s sent to their early IP partners.”

He said the foundries don’t have the resources to work to that same level with each and every EDA supplier so what is then occurring, particularly in the physical verification space, is the foundry will create their design rule manual and their regression test suite. Then the other EDA vendors have to go off and create their decks to try and match what the foundry has put together and understand as being accurate. “It’s not like every soccer player gets a trophy at the end of the season. Due to resources, they have to pick who their front runner is and partner with them to develop their process, and everybody else needs to match that.”

Decoding messages
Each time a new PDK is ready, each of the top three EDA vendors issues a similar announcement about how they are qualified. But are they all qualified to the same level?

Mentor Graphics’ White said, “For 16nm, TSMC did a big press release at the last DAC for deck release version 1.0 qualification for all the EDA suppliers. You saw a press release from Mentor saying that, you saw the same thing from Synopsys and Cadence. We did the same thing with Intel back at DAC timeframe where you saw three parallel press releases that Calibre is qualified for 14nm, and the same thing for the other guys. The thing that’s left unsaid is what deck was available 18 months before when they were first building their IP, when, let’s say, the lead customers were doing their initial test chips to that foundry. They were using a 0.5 version of the decks and so on. At that point in time, there’s only one supplier that’s qualified and available in that timeframe. For example, a company in San Diego, a company on Infinity Street in the Bay Area that sells phones, and even a big phone manufacturer in Korea — those companies have already released or are well down the road to building their next-generation products. They would have used only one supplier. So when you see the press releases say, ‘We’re qualified for XXX technology node,” yes, everyone is qualified but one of those suppliers actually has 100,000 miles of use on them and is the internal tool used by the R&D group of that particular foundry; the other two aren’t.’”

The question for the fabless company is what rule deck they started working at. What version of the deck were they using? What EDA tool were they using when they started the IP development? The question to a foundry is what tool does their internal R&D team use, because the answer to that question will indicate which tool was used to develop the new process, he continued.

Finally, as the early adopters move to advanced nodes, Mentor’s White concluded, they need more training than they did historically on how to run the physical verification tools. This makes it essential at 20nm and below to have a three-way NDA between the foundry, the fabless company and the EDA supplier. There are always unforeseen interactions between the foundry deck, the fabless design, and the EDA tool to provide training on how to use the foundry’s deck for a particular design style, for instance.