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AI Chips Driving Need For New Test Implementation Methodologies

A hierarchical test methodology can take full advantage of massively repeated cores in AI designs.

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Artificial intelligence has never been more in the news than it is today.  From picking stock market investments to autonomous driving, we have heard about what AI can do when it works and what happens when it goes awry. The consequences are huge if AI doesn’t work which puts a lot of pressure on hardware engineers to ensure that their chips can be extensively tested for proper and safe functionality.

AI chips’ biggest impact on test arises from a significant increase in design size which affects an EDA tool’s ability to process them in a flat design manner. This becomes an increasingly difficult, if not impossible problem to solve.      Also, the trend towards integrating cores from different design teams and IPs from external IP providers into a single chip has resulted in a system-on-a-chip (SOC) architecture and a methodology which employs widespread core reuse A hierarchical strategy for design and test is necessary to achieve a successful implementation in a timely manner. Synopsys TestMAX addresses the challenges in supporting DFT as part of a hierarchical flow.

A hierarchical methodology requires the design to be partitioned into cores. In the case of large processors such as AI and GPU, these cores are repeated instances. A hierarchical test methodology can take full advantage of massively repeated cores since the flow is only applied once per unique core and then, by definition, it is reused in all instances. A typical hierarchical flow using Synopsys TestMAX is illustrated in the figures below. It begins with analyzing each core using TestMAX Advisor, generating and inserting DFT logic with TestMAX Manager, isolating the core and synthesizing scan chains with TestMAX DFT and generating patterns with TestMAX ATPG (Figure 1).


Figure 1: Core Flow

Once the cores are complete, they are integrated into the top-level where scan chains may be synthesized along with scan compression and any other DFT IP (Figure 2).


Figure 2: SOC flow

Partitioning the design into multiple cores allows DFT to be implemented in parallel. A divide- and-conquer approach allows the cores to be handled in parallel with other cores. Once the core is complete all instances are also complete, saving significant processing time. As part of the flow, these cores are wrapped with an isolation ring which allows them to be tested independent of the other coresaves significant time in ATPG pattern generation since the amount of data being processed is greatly reduced compared to a flat, full-chip ATPG pattern generation. This methodology enables the work to be distributed amongst teams which may be in various locations, no longer requiring a centralized team until the top-level flow of the SOC begins. Having independently testable cores also provides more diagnostic resolution, simplified ECO processing and allows tools to operate with significantly decreased memory usage.

Once the cores are complete, they are integrated into the SOC. The advantage here is that the complete design does not need to be compiled at the SOC level. Due to the core isolation, the only logic needed at the SOC level are the core interfaces. At this level, a minimized gray-box representation of the core is used to test the SOC. The cores are put in external-test mode (EXTEST) where only this interface is compiled during verification.

This hierarchical test scheme enables the test patterns from the lower level cores to be used at higher levels without regeneration of the patterns.  The patterns just need to be ported to the next level and the setup controls mapped using a method called pattern porting. For this to work properly, a single test interface must be used. IEEE 1687 and 1500 protocols at the core and IEEE 1149.1 at the SOC are commonly used.

Applying hierarchical test methods is the best approach to handling large, complex SOCs, especially those with many repeated cores. Synopsys TestMAX family of test products provides this capability starting with RTL and DFT to placement-aware scan and testpoint insertion and on to place and route and GDSII, taking advantage of the transfer of information between all aspects of the flow.

For more information on the Synopsys family of test products, download our whitepaper “Redefining Expectations for Test”.



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