AMS Challenges Growing

High-k/metal gates and double patterning add to the challenges; but with AMS playing a bigger role in energy-saving measures opportunities grow.

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By David Lammers
Analog and mixed signal (MS) devices will play an ever-increasing role in saving energy, particularly as the “Internet of Things” expands to about 10 billion units per year over the next decade. But as leading-edge design rules scale to 28nm and below, enhanced with high-k/metal gate technologies, it is becoming increasingly challenging to integrate AMS devices on SoCs.

Tyson Tuttle, chief operating officer at Silicon Laboratories, said demand for mixed-signal technology will accelerate in an energy-conscious world. As people turn to electric vehicles, solar energy, and the “Internet of Things,” mixed-signal sales will increase sharply. “People will pay money to save energy,” Tuttle said at a Global Semiconductor Association (GSA) event held in Austin, Texas. For example, the embedded devices that rely on harvested energy, such as electricity harvested from vibrations, will become a multi-billion-dollar opportunity over the next decade, Tuttle said.

Increasingly, the “digital-centric” approach to AMS functionality is being employed to improve power consumption. AMS “enables new ways of managing energy and resources,” he said, citing smart meters, which deliver real-time monitoring of power consumption as one example.

Mixed-signal devices are about one-tenth of the $300 billion chip industry now.

Silicon Labs has shipped about a billion radio chips, which provide the FM radio function on handsets, personal media players, and other systems. The company is gaining traction in the integrated CMOS TV tuner market, which Tuttle said “is a hard problem” due to multiple broadcasting standards, noise margins, and other challenges.

While the topic of the event was the confluence of AMS and 28nm technology, few are close to the leading edge for largely AMS products. Silicon Labs uses relatively relaxed design rules (55nm at 2.5V is the most advanced process, and 90nm is common for chips with embedded flash). Tuttle said “it will be a while” before the TV tuner chip goes to 45nm technology, for example, partly because of mask costs. “There is no one application or chip right now that will pay for a 28nm mask set.”

While digital and analog use much different process technologies, digitally-assisted mixed signal hews closer to the leading edge. (Source: Silicon Laboratories)

AMS technology is becoming more challenging at 28nm. At the GSA event, only a few hands went up when the panel moderator—Mahesh Tirupattur, executive vice president of Analog Bits—asked how many people in the audience were designing at 28nm design rules. Jose Alvarez, design collateral manager at Freescale Semiconductor, said his company has several 28nm SoC designs underway.

“There is a significant amount of analog work, a lot more than we originally thought,” Alvarez said during the panel discussion on the challenges of 28nm AMS technology. As SoCs move to fast Serial I/O buses, design teams are being challenged. Clocking of the dozen or more phase locked loops (PLLs) is “very complex,” he said. Packaging is another challenge, he said, noting that 3D stacked ICs may be used to incorporate “high-end analog into low-end SoCs.”

3D and 2.5D (interposer) integration will provide “a boon for MS integration if the thermal issues can be worked out. I think we’ll see a lot more 3D packaging at 28nm and below,” he said.

“Today’s complex SoCs are throttled by power considerations,” Alvarez said. Putting circuits to sleep is one solution, but the design challenge is “putting the hooks in there to make sure those circuits come back to life” in a timely fashion.

Ana Hunter, in charge of Samsung’s U.S. foundry operations, said Samsung has several 28nm SoCs in the prototyping phase now, with 20nm devices headed toward shuttles, all including extensive AMS technology.

The panelists agreed that HK/MG and double patterning provide additional challenges. While HK/MG technology will reduce gate leakage, the metal gates result in increased variability, requiring more stringent circuit simulations. Similarly, double patterning introduces adjacent metals, oftentimes on different masks, which requires improved static timing analysis to ensure that the timing circuits work correctly. Extra margins and restricted layouts may be required.

The result is increased spending on AMS IP. Sanjay Krishnan, a management consultant at Keystone Strategy Inc., said about 40 percent of the intellectual property (IP) owned by foundries is analog mixed signal (AMS), while only 30 percent is digital IP. Foundries such as TSMC and Global Foundries are building up their AMS IP libraries in order to “add value like Apple did, creating their own ecosystems.”

“As AMS moves to the foundries, IP becomes more important,” Krishnan said. “The industry is evolving, going to more external IP. It is all part of the disassociation of the supply chain,” he said.