Architecting For Optimal Interface IP Integration

Experts at the table, part 3: Interposers; vertical stacking; impact of the packaging decision; analyzing noise.

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Semiconductor Engineering sat down to discuss the design and integration of complex interface IP with Ty Garibay, vice president of engineering at Altera; Brian Daellenbach, president of Northwest Logic; Frank Ferro, senior director of product management for memory and interface IP at Rambus; Saman Sadr, director of analog design at Semtech; and Navraj Nandra, senior director of marketing for analog/mixed signal IP and embedded memories at Synopsys. What follows are excerpts of that discussion. For part one, click here. For part two, click here.

SE: What happens in the design and integration of complex interface IPs in the realm of 2.5D designs?

Garibay: Altera has chosen not to participate in 2.5D yet as a product. We’ve done a lot of research with wafer scale interposers and it turns out that’s unfortunately not a great technology for FPGAs because we tend to build reticle size chips that happen to be almost wafer scale when you’re talking 65nm wafers. It’s clear that it’s a technology that is almost there. The reason we think tha there’s some real benefits to be had here is that in particular with the analog development with the finFET processes has proven to be very difficult to reach very high performance that is possible that the 16 and 14nm generations just arent’ ever going to be really good candidates for high speed – power efficiently, area effeciently, cost efficiently. Maybe it makes sense to keep things at 20nm for a little while and then refocus on 10 and make sure the foundries recover some of the device characteristics that analog needs so it will be easier to design. We see the stacked memory technologies driving the 2.5D very aggressively for this coming year, and we’ll see where it goes from there.

Ferro: From a controller standpoint, how does this effect you? Do you deal with that much?

Garibay: We’re a couple layers removed from the package, so it’s a little hard to comment as broadly, but what I can say specifically about HBM (because that’s a technology we have implemented) what we see clearly is there doesn’t look like there’s going to be a DDR5 standard. You can’t get it wide and fast, any wider or any faster, so what do you do? You go higher rates, serial, that’s what Hybrid Memory Cube is. Or you go more signals at about the same rate — that’s what HBM is — and the market is tussling now. Which of these technologies are really going to succeed in the marketplace and there isn’t clarity on that yet, so as a digital IP company, what we have to do is be there no matter who wins. The HBM standard is nice in that it’s not that much of a departure from the DDR3 types of things so we were able to basically further configure and enhance our base. We’ve created a database that has the ability to extract out of that database a variety of controllers. And now we have the capability to pull an HBM out of that database. That will be demonstrated in silicon with an FPGA in the next bit and we’ll see if that technology can succeed in the marketplace because it’s hard to use. People know how to take a board and put discrete devices on but to do 2.5D types of packaging, there’s going to be limited marketplace for that — it’s not going to be super-mainstream, so it will interesting to see how that all plays out.

Ferro: There is also the fingerpointing potential and as you add bill of materilas, if one part is bad, then the whole thing is bad. That’s a challenge too.

Nandra: From a physical IP perspective, whether it’s 2.5D or 3D, we don’t really see much of an impact to something like USB or a SerDes technology becuase maybe the capacitive characteristics change on the pins but there’s nothing fundamentally we have to change — it just gets oriented differently or placed differently but overall you’re not changing anything fundamentally.

Garibay: With 2.5D, it reduces the cap on the interface so much you can use to using normal thin oxide — if it’s physical you can pack those very, very tightly so really the limitation comes to be micobump spacing in either technology – either the interface technology or going straight up — so the density of the microbumps is something that we’re really fighting at this point: what’s manufacturable.

Nandra: I agree. I’ve looked at the interposer technology solution, and for me the challenge is the pitch of the microbumps — there’s overhang. It doesn’t matter how much we pack the IP.

Garibay: We’re going to put pads out over here.

Nandra: Yeah, so it’s like, why should I go to the effort of packing the IP.

Garibay: That’s an initial problem we’re having. You try to floorplan these big chips, and try to put these interfaces on the physical layout of the interfaces is this big, and the bumps are this big, so you have to architect something that can sit underneath the bumps that doesn’t want bumps, and talks into the chip. You have to find what can sit there and not waste that silicon.

SE: What is the impact the impact of the packaging decision of the development of IP? Do we have a way to capture this information and make it useful for more people in the design team?

Nandra: We do package modeling as part of our understanding of how to build the IP. You just acquire expertise in the team that we call package guys that are in the IP company so there is a database of knowledge that gets shared. It’s funny, I was walking in this morning and one of our partners that does packaging and board stuff for us came to me very excitedly to tell me that our USB 3.0 now has been requested by one customer to work on a two-layer board. I thought four was aggressive, so I just said, good luck! The point is that customers are continuing to drive cost down and somehow someone is going to figure out how to do this.

Sadr: Package design is an integral part of custom interfaces — you can’t really detach the two. Right now if you look at any type of channel model — the very connection that the circuit is making with the channel…the discontinuity is becoming the challenging part. How to really take that signal out and bring it to the outside world, that’s where packaging comes in. Typically, as a part of rethinking the technology, this has to be considered at a very early stage in the design. The choice of what type of package, how many layers, where the I/Os go is important.

SE: As a physical iP provider, how do you deal with all of the different packages that a customer might choose?

Ferro: We provide a specfication on the performance and then make an assumption. A lot of times we’ll assume worst-case package conditions and the customer might say, gee, your IP doesn’t look very good. We’re assuming you’re going to have a really bad, noisy package that we have to deal with so as we understand the package then we can go back and give much more accuracy. We have to look at the effects of the package — we even put circuits on the silicon to look at power supply noise and other noise that’s introduced to the system. We can leave it off for production for certainly for all of our test chips, we’ll have it so you can monitor noise and inject noise to get a much better view. Especially when you try to do probing, it doesn’t work so well, especially as we talk about 2.5D and 3D packaging, you can’t look at those signals anymore so you have to have another way to look at the noise introduced by the package or other sources.

Nandra: We do a similar approach where we have a noise generator — a giant gated clock tree generates a lot of thermal disturbance to the substrate. What’s interesting is it’s not always a substrate that’s the culprit. It can be what’s on Vdd. Then you can put a step function on there — sine waves. There are Ph.D.’s on this. Which one’s worse? Usually the step function is worse because it contains all the harmonics. You have to do that because we actually don’t know what our customer’s going to do with the IP, and sometimes they don’t do the most sensible things in terms of placement.

Sadr: That’s why package design and integration becomes an integral part of the whole IP design. We have our own signal integrity team, the packaging guy that actually looks into everything. This is typically the very first call after engagement, or even sometimes before the engagement, that our signal integrity people sit down with the customer’s signal integrity specialists and go through all these items.

SE: That’s a lot of overhead.

Nandra: There’s way more overhead if their chip doesn’t work.



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