Architecting For Optimal Interface IP Integration

Experts at the table, part two: The challenge of inductor-based IP at 14nm; hard IP requires different methodology; strong discipline in engineering teams; power gating in FPGAs.


Semiconductor Engineering sat down to discuss the design and integration of complex interface with Ty Garibay, VP of engineering at Altera; Brian Daellenbach, president of Northwest Logic; Frank Ferro, senior director of product management for memory and interface IP at Rambus; Saman Sadr, director of analog design at Semtech; and Navraj Nandra, senior director of marketing for analog/mixed signal IP and embedded memories at Synopsys. What follows are excerpts of that discussion. For part one, click here.

SE: What about inductor-based IP? Are IP providers supplying this today?

Nandra: Yes, in fact anything above 8Gb and with any kind of good face noise capability, these need to be inductive.

Garibay: That’s been an interesting challenge at 14nm.

Nandra: You can do things, and it really depends on the fab as well. There are different FinFET fabs unfortunately. I wish these guys would actually have worked together a few years ago to develop a baseline FinFET process — but that’s not the case. What we’ve seen is that the quality of inductor depends on the thickness of the top metals and the amount of eddy current that you can stop from flowing down into that substrate, so depending on the dielectric thickness…you can actually get a pretty good inductor but you’re right, you’ve got to think about these things. And there’s no real fast tool that can actually help you model the inductive characteristics so you’ve got to go through a 3D field solver, which takes a very long time and it’s all finite element analysis type simulations that take a very long time. You’ve got to wait for those to finish then you’ve got to extract them and put them into your favorite SPICE simulator, then you can do some SPICE. The foundries are not so open about providing these models for the inductors because they’ll provide the models and the devices — the transistors and the resistors, maybe some special capacitors — but when it comes to inductors and varactors, it’s a challenge with them.

SE: Why is it a challenge?

Nandra: It’s very tuned for a particular application, and as IP companies we do have some leverage we’ve worked together with the foundries to get these things but when you’re supporting multiple technologies, multiple different frequencies, a library of 100 different inductors — that’s a lot of overhead for the foundries to support as well.

SE: With the smaller geometries, what is the impact of that technology on the details of that process compared to another process?

Ferro: That’s the challenge of hard IP. There’s no baseline process and for every foundry, it’s not a simple port today.

Sadr: The key thing right now is that it requires a different methodology. The difference between the finer technologies versus FinFET technologies it requires a different methodology — it’s more like a layout for schematic. Secondly, co-development between the schematic and layout at the beginning, and now that is part of the methodology that has to be introduced. Another angle right now is as you are designing faster things, you are getting more sensitive to layout effects and the parameters of the technology that are one way or another you have to do iterations on, so at the end of the day, it makes your design cycle longer. So you must approach this systematically. EDA tools can help with this. Also, try to limit everything to more modular design — both at the macro level and also at the device level. Try to minimize the variations as much as possible. The designers, rather than dealing with the true analog nature of the design, which meant you could use anything, now they are limited to modules that they have to find variations of.

Nandra: We’ve enforced quite a strong discipline in our engineering team to follow a methodology. We’ve got a lot of engineers doing analog/mixed-signal IP — about 850 now — just doing analog/mixed-signal IP, so that’s a big organizational exercise so we’ve put a CAD infrastructure in place which uses our tools but also in-house tools. There is absolute discipline in place about how you bias devices — in order to get performance, sometimes you want to push devices into a region which gives you performance but isn’t manufacturable or gives unreliable manufacturing characteristics. So there’s a lot of good engineering practice that comes into building IPs on many different process nodes.

Daellenbach: As the technology nodes are going down, digital IP has less of an impact on power but still power is important. And power from a digital perspective can’t be solved just by doing a better digital design, you have to do it from an architecture perspective then it becomes a challenge of can we get ourselves into the shoes of our customer and understand how are they trying to solve a problem overall and how can we then trade digital IP that will fit into their solution so they can manage power. How can we get timing closure because digital IP, the guys have got enough problems with analog IP, the digital IP had better be pushbutton, I don’t have to worry about it IP. But then if it’s got too much latency then that’s not good either.

Nandra: You have to make the tradeoffs like, for example, with the L1 substates in PCI-Express. You’ve got three different substates, you’ve got to tradeoff power against latency. I’m seeing a lot of discussions around implementing power gating, for example. You do that on the digital side, you do it on the PHY side, and then you’ve got to figure out a way of sucking in all the information on the digital side in terms of the power states and power gating into the hard macro. And that blows up the size of the hard macro. I was really surprised when I saw the estimates that we were getting and adapting the hard IP to power gating. On the digital side, it’s not impacted.

Garibay: And for an FPGA, it just doesn’t work. They’re so dense that when you try to put those switches in…

Nandra: But customers are demanding it now, right?

SE: How do you handle that?

Garibay: It’s difficult. When you go to an FPGA customer and say we want to help save power by turning off some of the logic elements, it’s kind of like when you try to sell an IP, and say I’m going to help you save power by only letting you use 75% of what you paid us money for — it’s kind of a bittersweet thing. Every customer wants to believe that they’re perfect designers and that they’re going to just fill that thing perfectly and they don’t want to worry about power gating. And in FPGAs because you can’t do clocks in any effective way, that whole part of the design methodology is overboard other than what we do in the hard physical side. The power savings come from the very first decisions about how to do the fabric, how to do the hard IP — those choices make all the power difference.

SE: When did power gating become something that was critical to be able to do in FPGAs?

Garibay: Right now we really can’t do it very well but we’re hoping to do in our next generation architecture. I come from a mobile world so I’ve lived through bringing power gating in from 2001 to now, where it is just part of the architecture so it was interesting to me to transition into FPGAs and go, ‘Oh, we don’t do any of that.’ We think that we can do it architecturally but I think it’s going to be market segmented: probably in the low end market segment, where they’re more willing to think of something as a microcontroller and tune it, etc.; at the high end it’s a data pump. If you’re pumping 400Gbps Ethernet backplane, the last thing you want to do is worry about it — it’s in a big box in a big room with a big fan.

Nandra: We’ve got customers that are taking our IP into big chipsets for cellular applications and they’re concerned about getting the Energy Star label. There is a lot of discussion about the cost of the fan, the costs for the cooling. As a sidenote, we do a lot of verification of the IP, and the most expensive cost we have is keeping our server roooms cool. It’s that infrastructure cost. So there is this push of building high speed stuff, with some kind of concept of power optimization, and some of these new startups I’ve seen trying to build microservers, their whole pitch is that their engineers come from the mobile world and that’s why they can build microservers with low power.

Sadr: Power gating is not something new; it is making its way to the copper and wired communications world, but there was a good point made about it: you have to really look into the total power consumption of the system. You cannot design anymore an IP in isolation without understanding the compromises of the system.

SE: What’s the best way to capture that?

Sadr: It is a dialogue that has to happen very early on. As of today, there’s not one solution because with power gating you can put it on the chip, you can put it off the chip, you can put it in the digital — each has its own tradeoff. How do you address the tradeoffs is one of the challenges of this market segmentation.

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