Well-correlated power numbers and faster iterative changes to ensure data integrity.
This white paper proposes a new automated input qualification methodology that Arm developed using Siemens EDA’s PowerPro software portfolio that performs various data integrity checks at the IC design build and prototype stage. This methodology ensures in quicker iterations that input data are high fidelity, leading to a well correlated power numbers. Should multiple iterations be necessary, a checkpoint database method is implemented to bypass the clean stages of the tool run so that further analysis is only required for areas with power violations – enabling fast iterative refinement.
Various checks pertaining to activity annotation (FSDB/SAIF/STW/QWAVE), technology libraries (.lib) and parasitic mapping (SPEF) are already a part of PowerPro. With PowerPro defining an input qualification methodology around these checks, much like Arm, users can save up to 88 percent of project time in achieving reliable power numbers.
To read more, click here.
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