Using a consolidated verification mechanism to access all instances of a target design.
UPF provides a powerful mechanism to define a custom PA checker or assertion and provides a layer to completely separate it from design code. This is done by embedding the binding of the design and checker within the UPF file through the bind_checker command and its options. As a result, it provides a consolidated verification mechanism and allows Questa PA-SIM to access all instances of a target design with a custom checker within the current scope.
To read more, click here.
Next-gen lithography technology resurfaces for a variety of tasks.
So far there are no tools and no clear methodology to eliminating bugs. That would require understanding what an AI bug actually is.
This more than Moore technology is still ramping up, and problems need to be solved, but it could lead to some fundamental changes.
Why this technology approach is suddenly getting attention, and what hurdles still remain.
How electric vehicles, autonomous driving and car sharing are impacting chip design.
As advanced-node chips are added into cars, and usage models shift inside of data centers, new questions surface about reliability.
Is the industry heading toward another hardware/software divide in machine learning? Both sides have different objectives.
Cost of porting tools and IP will limit choices at partial nodes and create confusion at others.
This more than Moore technology is still ramping up, and problems need to be solved, but it could lead to some fundamental changes.
Are optimizations really a zero sum gain? Where to gamble and when to play it safe.
The race is on to simulate thermal and electromagnetic effects.
Why new approaches are needed to tie together training and inferencing.
Heat is becoming a bigger problem for chips developed at new process nodes and for automotive and industrial applications.
Leave a Reply