Using a consolidated verification mechanism to access all instances of a target design.
UPF provides a powerful mechanism to define a custom PA checker or assertion and provides a layer to completely separate it from design code. This is done by embedding the binding of the design and checker within the UPF file through the bind_checker command and its options. As a result, it provides a consolidated verification mechanism and allows Questa PA-SIM to access all instances of a target design with a custom checker within the current scope.
To read more, click here.
Experts at the Table, part 1: Shrinking features isn’t enough anymore. The big challenge now is how to achieve economies of scale and minimize complex integration issues.
Rising costs and gaps in equipment emerge as technology scales; new tools under development.
Explosion of data is forcing significant changes in where processing is done.
EUV is the clear winner down to 5nm, but what comes after that may be a combination of tools and techniques.
2019 will be a year of change for the semiconductor industry as new fields drive technological advancements.
This new communications standard could transform architectural decisions across the industry, but not right away and not necessarily in obvious ways.
What hoops will designers have to jump through to avoid concurrency bugs?
Why managing power is becoming more difficult, more critical, and much more expensive.
Analog circuitry stopped following Moore’s Law a long time ago, but that hasn’t always helped.
Is it possible to reduce the power consumed by memory by 50%? Yes, but it requires work in the memory and at the architecture level.
Can mixed-signal architectures boost artificial intelligence performance using less power?
When going to a smaller node is no longer an option, how do you get better power performance? Several techniques are possible.
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply