ASMC: TSVs Needed as Scaling Challenges Mount

By David Lammers
With the industry facing challenges in the introduction of EUV lithography and high costs for double patterning, TSV introductions have taken on heightened importance, participants said at the SEMI Advanced Semiconductor Manufacturing Conference (ASMC), held in Saratoga Springs, N.Y. in mid-May.

Risto Puhakka, president of market research firm VLSI Research Inc., said the gradual shift to both finFETs and TSVs will bolster equipment spending over the rest of this decade. “FinFETs will have a very dramatic impact on equipment spending, and wafer fab equipment spending will rapidly move to support 3D,” Puhakka said at the ASMC meeting.

Due to their initial high costs, however, TSVs will be adopted initially for performance reasons. By 2016, VLSI Research expects that TSV-connected chips will account for almost $12 billion in revenues. While that is a significant number, he noted that it will account for only about 5 percent of the sub-45nm silicon shipped in 2016. By that year, TSV-related equipment revenues will total $940 million, much of it for plating and etch equipment, he said.

Because of the relatively high cost of adding TSVs – an average of about $400 per wafer, double the normal packaging costs, according to VLSI Research – usage will be concentrated in high-performance chips, such as FPGAs, CPUs and GPUs, and application processors, and not in commodity DRAMs.

Overall, the semiconductor industry is in a healthy period, with VLSI Research expecting an average growth rate of 5-8 percent over the next several years, higher than the worldwide GDP increase. In 2011, IC revenues were $252.4 billion, which he said is expected to increase to $342.8 billion by 2016.

Equipment sales also are on an upward track, ratcheting up from about $50 billion last year and this year to $67.3 billion in 2016, he said. However, Puhakka qualified his remarks at the outset, saying his forecasts could be disrupted if Europe has a financial crash, or what he called “Europe’s Lehman Brothers moment.”

Michael Campbell

Michael Campbell, senior vice president of engineering at Qualcomm, said, “We have to go smaller, whether it is by stacking or shrinking.”

“EUV will come, and we are betting on 2014 or 2015. But there are limits to how we can do the 14nm generation cost effectively. There are cost barriers with double patterning/double etch, but we still don’t know if EUV will get there. It sounds ugly,” he said in a keynote speech at ASMC.

Transistor scaling will continue, bolstered by a shift to finFETs. And Campbell said tests of a 0.18 micron SOI process for power and radio functions have shown “really cool” results.

Noting that many of the functions of a cellphone chip set, including memory, power management, and RF, could be stacked vertically, Campbell said. “As a system solution for consumers, TSVs have a lot of interesting potential.”

Subramanian Iyer, an IBM fellow who has managed IBM’s embedded memory and several other programs, took a similar view toward TSV-enabled 3D chips: arguing that the performance benefits are real, but remaining uncommitted about when the technology will be introduced.

IBM has been hiring more engineers to accelerate its 3D programs, participants at ASMC said. (Prof. James Lu, a packaging guru who teaches at Rensselaer Polytechnic Institute, said demand for his engineering graduates is so high that “I need to graduate more students.”)

But Iyer declined to say when IBM will introduce a TSV-connected product, though he showed a slide of a processor connected to a memory chip underneath with TSVs.

Iyer said the thinned wafers tend to bow, adding difficulty to alignment and processing. “Wafer bow is still the biggest technical issue. Overall, we have to get the costs down,” Iyer said.

The bandwidth and performance benefits from dense TSV connections are real: Iyer said 30 percent of total power consumption is in “chips talking to chips” over long traces on a printed circuit board. Book-sized printed circuit boards can be reduced to a 50-by-50 mm size with TSV connections between the MPU and the memory.

SOI Embedded Memory

Iyer said the semiconductor industry is in “a new age of non-optimal scaling” in which performance and power do not improve as much as in past generations. IBM found one answer in an SOI-based embedded DRAM technology.

“Scaling is becoming quite difficult, with expensive development costs. The benefits are still there but the improvements are saturating. And every generation is more complex,” said Iyer, who has worked at IBM since 1981.

He said EUV lithography will not be available at the 14nm node, and the industry is still “debating its use for 10nm.” During an ASMC panel discussion, he suggested that if EUV is not ready for the 10nm node, it may be essentially too late, as CMOS itself may run out of scaling room after the 7nm node.

Already, the DRAM stacked capacitor is “dead,” Iyer said. That may be one reason why TSMC announced at its recent technology event that it will no longer develop an embedded DRAM technology for its foundry customers, with the move to TSV-connected DRAMs as a replacement going forward, TSMC managers said.

IBM, which began using SOI technology in 1998, found that it could develop a fast, low-leakage eDRAM on an SOI substrate. “Making a DRAM on SOI is a lot easier than on bulk,” Iyer said. “When we first made the move to SOI, we thought it would be terrifying. It turned out to be an immense process simplification.”

Using the buried oxide layer in SOI substrates, IBM could dispense with a thick oxide collar it had used to shut off parasitic capacitance in the pFET well. And implant steps were dispensed with by buying an SOI substrate with N+ and P- epi layers built-in.

IBM uses a deep trench DRAM capacitor, and builds 96 MB of cache on its latest Power processors for the Z series machines ( mainframes), estimating that those chips have 25 percent higher throughput than they would if only SRAM memory was available.

In addition, Iyer said “almost everything IBM makes” has an eDRAM component to it, and said IBM is open to licensing its SOI-based eDRAM technology. “If 10 percent of the die is SRAM, it makes sense to use eDRAM,” he said.