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Metal Thermal Interface Material For The Next Generation FCBGA


Thermal interface materials (TIMs) have been widely adopted for improved thermal dissipation in flip chip ball grid array (FCBGA), flip chip lidded ball grid array (FCLGA) and flip chip pin grid array (FCPGA) packaging. As the next generation devices' requirements for power get even higher, enhanced thermal performance at the package level is increasingly important. A typical TIM applies a poly... » read more

Heterogeneous Integration Using Organic Interposer Technology


As the costs of advanced node silicon have risen sharply with the 7 and 5-nanometer nodes, advanced packaging is coming to a crossroad where it is no longer fiscally prudent to pack all desired functionality into a single die. While single-die packages will still be around, the high-end market is shifting towards multiple-die packages to reduce overall costs and improve functionality. This shif... » read more

High Thermal Die-Attach Paste Development For Analog Devices


Authors: Kiichiro Higaki, Toru Takahashi, Akinori Ono from Assembly Engineering Department Amkor Technology Japan, Inc. Keiichi Kusaka, Takayuki Nishi, Takeshi Mori from Information & Telecommunication Materials Research Laboratory, Sumitomo Bakelite Company, Limited Daisuke Koike, Masahiko Hori from Package Solution Technology Development Department, Electronic Devices & Storage Res... » read more

Qualifying The ExposedPad TQFP For AEC-Q006 Grade 0


Semiconductor packages used in various vehicle applications require high reliability. As technological innovations in the automotive market increase, the demand for highly reliable packaging is increasing for applications in autonomous driving, human interfaces, electric vehicles (EVs), hybrid electric vehicles (HEVs) and more. Package reliability is essential because automotive packages must p... » read more

Wafer-Level Fan-Out For High-Performance, Low-Cost Packaging Of Monolithic RF MEMS/CMOS


Navigating the trade-offs between performance, size, cost and reliability can be a challenge when considering integrated circuit (IC) packaging and the end-application. The integration of micro-electromechanical systems (MEMS), either monolithic or heterogeneous, introduces yet another level of complexity that has only recently been a major focus of multi-device packaging [1]. Wafer-level fanou... » read more

Will An Adhesion Promoter Prevent Delamination In Power Semiconductor Packages?


Power semiconductor packages are used in high temperature, high voltage environments. With the increase of electric vehicles (EVs) and hybrid electric vehicles (HEV) in the automotive market, demands on (and for) power packages have been growing. Packages for automotive applications must pass extensive testing for safety, therefore, packaging reliability is essential. As more semiconductor pack... » read more

High Thermal Die-Attach Paste Development For Analog Circuits


In recent years, various die attach (DA) materials have been developed to cope with the higher power dissipation requirements of semiconductor devices. DA materials based on metals such as solder or sintered silver (Ag) are used for very high heat generating power devices. While they show outstanding thermal performance, the mechanical properties of these materials are less than ideal. This lim... » read more

Adding Value With Unit Level Traceability (ULT) In Automotive Packaging


Automotive product traceability has existed in one form or another for several decades. Traceability generally refers to tracking and tracing each component that comprises every subsystem in a car. Traditionally, this has been achieved with direct part marking on mechanical or electronic components, using 1D or 2D barcodes or radio-frequency identification (RFID). Since vehicle recalls are cost... » read more

Advanced Packaging For Improved Network Communications


The global demand for data increases day-by-day. At the same time, the data transmission rate will increase to exceed 1 Terabits per second (Tbps) near the middle of this decade. To address this situation and provide a third alternative, engineers are increasingly looking into the chiplet approach with multiple smaller dies integrated in a single package. Only the logic portion that needs to... » read more

Chip Board Interaction Analysis Of 22nm FD-SOI Technology In WLP


Recently, Wafer Level Packaging (WLP) has been in high demand, especially in mobile device applications as a path to enable miniaturization while maintaining good electrical performance. The relatively inexpensive package cost and simplified supply chain are encouraging other industries to adapt WLP capabilities for radio frequency (RF), communications/sensing (mmWave) and automotive applicatio... » read more

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