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Brian Bailey

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Brian Bailey is Technology Editor/EDA for Semiconductor Engineering.

Author's Latest Posts

Thermally Challenged
By Brian Bailey - 05 Dec, 2013 - Comments: 0

Chips run hot and the thermal densities increase with every reduction in fabrication geometry. “When we go down to 16nm the local power density increases by 25% and the local gate density also increases by 25% to 30%,” explains Norman Chang, vice president of product strategy at Ansys/Apache. In fact, this is becoming such a large problem that it is affecting the scaling process itsel... » read more

Powerful Software Optimization
By Brian Bailey - 05 Dec, 2013 - Comments: 0

It is commonly accepted that the higher you go in the design chain, the bigger the impact that design and implementation decision can have. While power optimization may have started deep in the silicon, the success of a product, such a smart phone, often is based on the time between charges. Batteries provide a finite energy resource, and while low-level optimization may focus on power reductio... » read more

Power-Performance Bits: Dec 3
By Brian Bailey - 03 Dec, 2013 - Comments: 0

In this week’s edition of Power/Performance Bits we look at two very different types of antennas, in one case a combined antenna and solar panel and in the second nanoantennas that can create holograms. Combining Antennas with Solar Panels When it comes to satellites weight is everything, and historically telecommunication antennas and solar cells have never really worked well together, a... » read more

System Bits: Dec. 3
By Brian Bailey - 03 Dec, 2013 - Comments: 0

Tagging is a way of organizing information and today’s System Bits looks at two aspects of tagging. The first is an algorithm associated with social media and the second about how the brain geotags information. New Algorithm Finds You, Even in Untagged Photos You cannot hide on the Internet anymore. Anything posted online can be found, although in the past photos that were untagged may ha... » read more

System Bits Nov 26
By Brian Bailey - 26 Nov, 2013 - Comments: 0

Scaling The Quantum Slopes Like any task, there are easy and hard ways to control atoms and molecules as quantum systems, which are driven by tailored radiation fields. More efficient methods for manipulating quantum systems could help scientists realize the next generation of technology by harnessing atoms and molecules to create small but incredibly powerful devices, such as molecular electr... » read more

Power/Performance Bits: Nov. 26
By Brian Bailey - 26 Nov, 2013 - Comments: 0

Many people are predicting that power will be the issue that brings Moore’s Law to an end. Power creates heat and that heat can be destructive to chips, so there are two paths forward – the first is to reduce heat and the second is to get it off chip. It seems as if magnets may be the common key to both approaches. Magnetic Transistors New work by researchers at UC Berkeley soon could t... » read more

Is There Light At The End Of Moore’s Tunnel
By Brian Bailey - 22 Nov, 2013 - Comments: 2

Electrons are slow, clumsy and quite easily distracted. They’re slow because it now takes a signal longer to cross a chip than the period of the clock signal. They often don’t travel in straight lines as they collide with other atoms. And electromagnetic interference between adjacent signals can mess with the information they are transferring. On the other hand, light has none of these p... » read more

Do Students Need More Formal Education?
By Brian Bailey - 21 Nov, 2013 - Comments: 0

A few weeks ago, some of the top researchers and practitioners in the area of formal methods converged on Portland, Oregon. The event was the annual Formal Methods in Computer-Aided Design (FMCAD) conference and Semiconductor Engineering attended the panel titled “Teaching Formal Methods: Needs, Challenges, Experiences, and Opportunities.” Panelists included: Jason Baumgartner, formal verif... » read more

Cracking The Tough Nut Using Formal Methods
By Brian Bailey - 21 Nov, 2013 - Comments: 1

Pranav Ashar, CTO of Real Intent, assured a packed room of researchers and practitioners of formal methods at the recent FMCAD conference: “Static verification is being used in the verification of designs. Every major chip out there is using static methods for sign-off today.” He used an analogy of cracking a nut. “There’s a right way and a wrong way and if you don’t pick the right me... » read more

Coming Up With The Wrong Formal Answer
By Brian Bailey - 21 Nov, 2013 - Comments: 0

It was a surreal moment. I was sitting in a conference room in Portland listening to a panel session about [getkc id="33" kc_name="formal"] methods. The topic was discussing the fact that there is insufficient education at the undergraduate level in formal methods and algorithmic approaches to verification. You can read about the panel here. In the question and answer session, a point was ma... » read more

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