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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Blog Review: Feb. 1
By Jesse Allen - 01 Feb, 2023 - Comments: 0

Siemens EDA's Harry Foster explores trends in low power design techniques for ICs and ASICs, with 72% of design projects reported actively managing power. Synopsys' Charlie Matar, Rita Horner, and Pawini Mahajan look at the concept of reliability, availability, and serviceability (RAS) in the context of high-performance computing SoC designs and how it can be supported with silicon lifecycle... » read more

Blog Review: Jan. 25
By Jesse Allen - 25 Jan, 2023 - Comments: 0

Cadence's Shyam Sharma shares some important design and verification considerations when working with DDR5 SDRAM and DDR5 DIMM-based memory subsystems, including reset and power on initialization, speed bin compliance, and refresh, RFM, and temperature requirements. Siemens EDA's Harry Foster examines trends in adoption of languages and libraries for IC and ASIC design, testbench creation, a... » read more

Research Bits: Jan. 24
By Jesse Allen - 24 Jan, 2023 - Comments: 0

Transistor-free compute-in-memory Researchers from the University of Pennsylvania, Sandia National Laboratories, and Brookhaven National Laboratory propose a transistor-free compute-in-memory (CIM) architecture to overcome memory bottlenecks and reduce power consumption in AI workloads. "Even when used in a compute-in-memory architecture, transistors compromise the access time of data," sai... » read more

Week In Review: Design, Low Power
By Jesse Allen - 20 Jan, 2023 - Comments: 0

Worldwide semiconductor revenue increased 1.1% in 2022 to $601.7 billion, up from $595 billion in 2021, according to preliminary results from Gartner. The combined revenue of the top 25 semiconductor vendors increased 2.8% in 2022 and accounted for 77.5% of the market. The memory segment posted a 10% revenue decrease. Analog showed the strongest growth, up 19% from 2021, followed by discretes, ... » read more

Blog Review: Jan. 18
By Jesse Allen - 18 Jan, 2023 - Comments: 0

Synopsys' Dana Neustadter, Sara Zafar Jafarzadeh, and Ruud Derwig argue that we are already at an inflection point for post-quantum security because devices and infrastructure systems with longer life cycles or communicating data that must be kept confidential for an extended period need to have a path towards quantum-safe solutions. Siemens EDA's Harry Foster looks at trends in adoption of ... » read more

Research Bits: Jan. 17
By Jesse Allen - 17 Jan, 2023 - Comments: 0

Ionic circuit for neural nets Researchers at Harvard University and DNA Script developed an ionic circuit comprising hundreds of ionic transistors for neural net computing. While ions in water move slower than electrons in semiconductors, the team noted that the diversity of ionic species with different physical and chemical properties could be harnessed for more diverse information process... » read more

Week In Review: Design, Low Power
By Jesse Allen - 13 Jan, 2023 - Comments: 0

With funding from the Semiconductor Research Corporation, a group of 10 universities is banding together to create the Processing with Intelligent Storage and Memory center, or PRISM, led by University of California San Diego. The $50.5 million PRISM center will focus on four different themes: novel memory and storage devices and circuits; next generation architectures; systems and software; an... » read more

Blog Review: Jan. 11
By Jesse Allen - 11 Jan, 2023 - Comments: 0

Cadence's Veena Parthan explains why in CFD, understanding the consequences of choices regarding the computational mesh is essential for generating high-fidelity simulation results. Synopsys' Chris Clark shares key considerations and questions to factor in when developing solutions for software-defined vehicles that must meet safety, security, reliability, and quality standards. Siemens E... » read more

Research Bits: Jan. 9
By Jesse Allen - 09 Jan, 2023 - Comments: 0

Making stretchy semiconductors Researchers from Pennsylvania State University, University of Houston, Purdue University, and Texas Heart Institute developed a new method to make soft, stretchable transistors easier and cheaper to manufacture. The lateral phase separation induced micromesh (LPSM) process involves mixing a semiconductor and an elastomer and spin coating the liquid mixture pre... » read more

Blog Review: Jan. 4
By Jesse Allen - 04 Jan, 2023 - Comments: 0

Siemens EDA's Harry Foster investigates the percentage of total IC/ASIC project time spent in verification and increasing engineering headcount, particularly growing demand for verification engineers. Synopsys' Stelios Diamantidis argues that retargeting older chips using AI offers a way to move chip designs between nodes and absorb the market’s excess capacity. Cadence's Paul McLellan ... » read more

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