Author's Latest Posts


Blog Review: Nov. 27


Arm's Ben Fletcher digs into what's needed to make wireless 3D integration a reality from a tool to automate the design and optimization process for inductors used in wireless 3D-ICs to exploring how the data can be encoded in the transceiver to reduce power consumption. Cadence's Paul McLellan listens in as Eli Singerman of Intel explains the importance of platform security and why firmware... » read more

Power/Performance Bits: Nov. 25


Rigid or flexible in one device Researchers at the Korea Advanced Institute of Science and Technology (KAIST), Electronics and Telecommunications Research Institute (ETRI) in Daejeon, University of Colorado Boulder, Washington University in St. Louis, Cornell University, and Georgia Institute of Technology proposed a system that would allow electronics to transform from stiff devices to flexib... » read more

Week In Review: Design, Low Power


Accellera formed the Universal Verification Methodology Analog/Mixed-Signal Working Group (UVM-AMS WG), which will work to develop a standard that will provide a unified analog/mixed-signal verification methodology based on UVM to improve the verification of AMS integrated circuits and systems. “Our objective is to standardize a method to drive and monitor analog/mixed-signal nets within UVM,... » read more

Blog Review: Nov. 20


Arm's Ben Fletcher points to research into a new low-cost alternative to through-silicon vias in 3D stacked ICs, particularly cost-sensitive IoT designs, where communication between silicon layers is completely wireless. Cadence's Paul McLellan checks in on the progress of DARPA's OpenROAD project to build a no-human-in-the-loop open source EDA flow for leading-edge nodes. Mentor's Colin ... » read more

Power/Performance Bits: Nov. 19


Quantum communications chip Researchers at Nanyang Technological University, Australian National University, A∗STAR, University of Science and Technology of China, Singapore University of Technology and Design, Sun Yat-sen University, Beijing University of Posts and Telecommunications, and National University of Singapore built an integrated silicon photonic chip capable of performing quantu... » read more

Week In Review: Design, Low Power


M&A eSilicon will be acquired by Inphi Corporation and Synopsys. Inphi is acquiring the majority of the company, including the ASIC business and 56/112G SerDes design and related IP, for $216 million in both cash and the assumption of debt. Inphi expects to combine its DSP, TiA, Driver and SiPho products with eSilicon’s 2.5D packaging and custom silicon design capabilities for electro-optics... » read more

Blog Review: Nov. 13


Applied Materials' Buvna Ayyagari-Sangamalli argues that the siloed structure that produced the computing eras of the past will not be sufficient to fuel the AI era and that a new codesign approach to everything from architecture to materials is needed. Arm's Wendy Elsasser examines emerging non-volatile memories and how they have triggered innovation for new memory protocols and optimized s... » read more

Power/Performance Bits: Nov. 11


Smaller DACs and ADCs Researchers at the National University of Singapore invented a novel class of Digital-to-Analog (DAC) and Analog-to-Digital Converters (ADC) that use a fully-digital architecture. This digital architecture means design time for sensor interfaces can be reduced from months to hours with a fully-automated digital design methodology, the team said. It also has the benefit... » read more

Week In Review: Design, Low Power


Cadence unveiled a static timing/signal integrity analysis and power integrity analysis tool, Tempus Power Integrity Solution, that integrates the Tempus Timing Signoff and Voltus IC Power Integrity signoff engines. Early use cases demonstrated it correctly identified IR drop errors, avoiding silicon failure prior to tapeout and improving the maximum frequency in silicon by up to 10%. Arasan... » read more

Blog Review: Nov. 6


Cadence's Paul McLellan considers why high-performance compute, high-performance networks, and security will all be vital to the next wave of devices and the importance of optimization. Synopsys' Taylor Armerding points to some best practices for assessing your supply chain to find the weak links that could lead to a security breach, from why to make it a priority to what to ask software ven... » read more

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