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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Week In Review: Design, Low Power
By Jesse Allen - 15 Mar, 2019 - Comments: 0

M&A Nvidia will acquire Mellanox for $6.9 billion in cash, the largest deal in the chipmaker's history. Traditionally a PC GPU company, Nvidia has made a push into high-performance computing, particularly for AI workloads. Founded in 1999, Israel-based Mellanox focuses on end-to-end Ethernet and InfiniBand interconnect solutions and services for servers and storage. According to Nvidia, Me... » read more

Blog Review: Mar. 13
By Jesse Allen - 13 Mar, 2019 - Comments: 0

Mentor's Tom Fitzpatrick questions whether deep learning approaches can really help improve coverage in modern, complex designs. Cadence's Paul McLellan listens in at MWC as Huawei chairman Guo Ping defends the company's security practices and shows where its heading in 5G. Synopsys' Eric Huang checks out the newly announced USB4 specification, changes to previous USB names, and a few things ... » read more

Power/Performance Bits: Mar. 11
By Jesse Allen - 11 Mar, 2019 - Comments: 0

Reading qubits faster Researchers at Aalto University and VTT Technical Research Centre of Finland propose a faster way to read information from qubits, the building blocks of quantum computers. Currently, they are extremely sensitive to disruption even in cryogenic environments, holding quantum information for less than a millisecond. In the method now used to read information from a qubit... » read more

Week In Review: Design, Low Power
By Jesse Allen - 08 Mar, 2019 - Comments: 0

Cadence debuted Denali Gen2 IP for LPDDR5/4/4X in TSMC's 7nm FinFET process technology. The offering consists of PHY, controller and Verification IP. It supports both the pre-release LPDDR5 standard and LPDDR4/4X devices as well as Arm AMBA AXI buses and reliability features like in-line error correcting codes. The LPDDR5 standard provides up to 1.5x bandwidth over LPDDR4 and LPDDR4X. The US... » read more

Blog Review: Mar. 6
By Jesse Allen - 06 Mar, 2019 - Comments: 0

Synopsys' Snigdha Dua traces the evolution of memory from SDRAM to DDR5 and the techniques that provide each generation's speed increase. Cadence's Paul McLellan digs into the challenges of 112Gbps SerDes, including what makes PAM4 signaling different from NRZ and what goes into equalization and modeling. Mentor's Rich Edelman provides a quick tutorial on how to set up a custom UVM report... » read more

Power/Performance Bits: Mar. 5
By Jesse Allen - 05 Mar, 2019 - Comments: 0

Solar chemical manufacturing Researchers at RMIT University, CSIRO Manufacturing, and University of Melbourne developed a nano-enhanced material that can capture 99% of light and use it to power chemical reactions. One of the world's biggest energy users, the chemical manufacturing industry accounts for about 10% of global energy consumption and 7% of industrial greenhouse gas emissions. In th... » read more

Week In Review: Design, Low Power
By Jesse Allen - 01 Mar, 2019 - Comments: 0

Tools & IP OneSpin Solutions debuted the Hardware Metric Calculation (HMC) App, which uses automatically extracted design information to calculate key hardware metrics to comply with functional safety standards. In particular, it focuses on automotive and autonomous driving SoCs needing to meet the highest functional safety requirements defined by the ISO 26262 standard. The HMC App calcul... » read more

Blog Review: Feb. 27
By Jesse Allen - 27 Feb, 2019 - Comments: 0

Mentor's Harry Foster checks out the trends in language and library adoption for IC/ASIC designs and finds increased adoption of SystemVerilog for both design and verification while UVM remains the dominant verification methodology. Synopsys' Taylor Armerding chats with Chris Clark of Synopsys and Tim Weisenberger of SAE about the weakest points in automotive security and why it's time to mo... » read more

Power/Performance Bits: Feb. 26
By Jesse Allen - 26 Feb, 2019 - Comments: 0

Integrated RRAM for edge AI Researchers at CEA-Leti and Stanford University have developed the first circuit integrating multiple-bit non-volatile Resistive RAM (RRAM) with silicon computing units, as well as new memory resiliency features that provide 2.3-times the capacity of existing RRAM. The proof-of-concept chip monolithically integrates two heterogeneous technologies: 18KB of on-chip... » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 Feb, 2019 - Comments: 0

Tools OneSpin unveiled a set of formal apps for development and assessment of RISC-V cores. The RISC-V Integrity Verification Solution formalizes the RISC-V ISA in a set of SystemVerilog Assertions to verify compliance for the ISA is met. It provides a formal bug absence core assessment environment for unbounded proofs and systematic discovery of all hidden instructions or unintended side effe... » read more

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