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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Blog Review: Oct. 16
By Jesse Allen - 16 Oct, 2019 - Comments: 0

Arm's Greg Yeric dives into the challenges facing the semiconductor industry and potential solutions that could possibly have huge impacts toward the year 2030, from DNA self-assembly to new physics, in an adaptation of his wide-ranging Arm TechCon keynote. Cadence's Paul McLellan considers Google's recent quantum computing achievement, what quantum supremacy really means, and where it leave... » read more

Power/Performance Bits: Oct. 15
By Jesse Allen - 15 Oct, 2019 - Comments: 0

Probabilistic computing Researchers at Purdue University and Tohoku University built a hardware demonstration of a probabilistic computer utilizing p-bits to perform quantum computer-like calculations. The team says probabilistic computing could bridge the gap between classical and quantum computing and more efficiently solve problems in areas such as drug research, encryption and cybersecurit... » read more

Week In Review: Design, Low Power
By Jesse Allen - 11 Oct, 2019 - Comments: 0

M&A Dialog Semiconductor will acquire Creative Chips for approximately $80 million cash, with contingent consideration of up to $23 million. The move will expand Dialog's Industrial IoT portfolio, adding Creative Chips' industrial Ethernet and other mixed-signal products for connecting large numbers of IIoT sensors to industrial networks. Based in Bingen, Germany, Creative Chips was founded in... » read more

Blog Review: Oct. 9
By Jesse Allen - 09 Oct, 2019 - Comments: 0

In a video, Cadence's Tom Hackett continues his introduction to finite element analysis (FEA) and the important role it can play in electronics deign. Mentor's Colin Walls considers dynamic memory allocation in real-time operating systems and the problems of non-deterministic behavior and ill-defined failure modes. Synopsys' Taylor Armerding contends that ethical hackers are a necessary p... » read more

Power/Performance Bits: Oct. 9
By Jesse Allen - 09 Oct, 2019 - Comments: 0

Topological insulator waveguides Engineers at the University of Pennsylvania and Polytechnic University of Milan applied topological insulators to photonic chips to make reconfigurable waveguides. In topological insulators, charged particles can flow freely on the material's edges but can't pass through the interior. For photonics, topological insulators with edges that could be redefined m... » read more

Week In Review: Design, Low Power
By Jesse Allen - 04 Oct, 2019 - Comments: 0

Synopsys completed its acquisition of QTronic GmbH, a provider of simulation, test tools, and services for automotive software and systems development. Terms of the deal were not disclosed. Synopsys launched the PrimeECO design closure solution, a signoff-driven solution that the company says achieves signoff closure with zero iterations. The tool includes a machine-learning-driven Hybrid Ti... » read more

Blog Review: Oct. 2
By Jesse Allen - 02 Oct, 2019 - Comments: 0

In a video, Cadence's Tom Hackett explains finite element analysis by looking at a simple model of a bridge and showing why FEA techniques are required for analysis of real-world structures. Synopsys' Taylor Armerding examines why the 156-year-old False Claims Act has new relevance when companies are accused of failing to meet cybersecurity standards. Mentor's Colin Walls demystifies memo... » read more

Power/Performance Bits: Oct. 1
By Jesse Allen - 01 Oct, 2019 - Comments: 0

Nighttime power Researchers at UCLA and Stanford University created a low-cost device that harnesses radiative cooling to provide a small amount of renewable energy at night. While the device only provides a small amount of power, it could be useful for areas without reliable electricity or access to batteries. Radiative cooling happens when a surface that faces the sky emits heat as therma... » read more

Week In Review: Design, Low Power
By Jesse Allen - 27 Sep, 2019 - Comments: 0

eSilicon debuted its 7nm high-bandwidth interconnect (HBI)+ PHY IP, a special-purpose hard IP block that offers a high-bandwidth, low-power and low-latency wide-parallel, clock-forwarded PHY interface for 2.5D applications such as chiplets. HBI+ PHY delivers a data rate of up to 4.0Gbps per pin. Flexible configurations include up to 80 receive and 80 transmit connections per channel and up to 2... » read more

Blog Review: Sept. 25
By Jesse Allen - 25 Sep, 2019 - Comments: 0

Mentor's Dave Rich points out that unexpected values from a constraint solver can often be explained by how Verilog expression evaluation rules affect the solution space of SystemVerilog constraints. Cadence's Madhavi Rao points to the need for new and updated safety and cybersecurity standards for autonomous vehicles and highlights one of the most challenging parts of AV deployment. A Sy... » read more

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