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Week In Review: Design, Low Power

Arm adds custom instructions; Synopsys’ functional safety verification; 5nm certifications; CCIX spec; Adesto’s satellite deal.

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M&A
Dialog Semiconductor will acquire Creative Chips for approximately $80 million cash, with contingent consideration of up to $23 million. The move will expand Dialog’s Industrial IoT portfolio, adding Creative Chips’ industrial Ethernet and other mixed-signal products for connecting large numbers of IIoT sensors to industrial networks. Based in Bingen, Germany, Creative Chips was founded in 1999 and is currently developing a range of IO-Link IC products.

Tools & IP
Arm will add the ability to create custom instructions in the Armv8-M architecture. Initially available for Cortex-M33 CPUs, Arm Custom Instructions are enabled by modifications to the CPU that reserve encoding space for designers to add custom datapath extensions, enabling various types of accelerators optimized for edge compute use cases such as AI/ML and IoT. The feature will be available in the first half of 2020 for no additional cost. Arm also outlined its new approach to IP design that focuses on use-case driven optimization. The Total Compute approach focuses on optimizing performance, security, and developer access as an integrated solution.

Synopsys debuted a new functional safety verification solution, VC Functional Safety Manager, to reduce time to ISO 26262 certification for automotive IP and semiconductor companies. The tool provides automated FMEA/FMEDA and fault classification as well as access control, audit trail, and individual component-based version/revision control.

UltraSoC announced a new line of hardware-based cybersecurity products. The first, Bus Sentinel, monitors and controls the internal bus of an SoC to observe how the chip’s interconnected sub-blocks are interacting. It can be configured to detect specific transaction types and respond to threats in a variety of ways in real time.

Mentor’s Questa simulation tools have been optimized to run on a 64-bit Arm Neoverse-based server platform, either in cloud-based environments or as part of an on-premise parallel regression grid. The move is part of a broader push by the company to enable its EDA tools for Arm-based servers.

Cadence teamed up with Samsung Foundry and Arm on a digital implementation and signoff full flow for the rapid implementation of the next-generation Arm “Hercules” CPU using the Samsung Foundry 5nm Low-Power Early (5LPE) process technology. Implementation is based on Arm 5LPE performance-optimized libraries and memories. A corresponding rapid adoption kit (RAK) is available.

Synopsys’ Fusion Design Platform was certified for Samsung Foundry’s 5LPE process and has been optimized for Arm’s next-generation “Hercules” processor. A QuickStart Implementation Kit (QIK) with scripts and reference guide is available for Arm advanced core adopters. Additionally, Synopsys’ Fusion Design Platform was certified for GlobalFoundries’ 12nm Leading-Performance (12LP) FinFET platform.

Mentor’s Tessent software suite was certified for Samsung’s 7nm Low Power Plus (LPP) technology.

The CCIX Consortium published the CCIX Base Specification Revision 1.1 Version 1.0 with support for the PCIe Base Specification Revision 5.0 Version 1.0 and transfer speeds of 32GT/s. The revision is backwards compatible with 1.0.

Adesto Technologies is engaging with the European Space Agency (ESA) through the agency’s ARTES Competitiveness and Growth program to develop technologies for next-generation mobile satellite communications. In particular, the work will focus on the Ku and Ka frequency bands. Adesto will develop innovative technologies including a new receiver architecture, IP blocks for satellite and 5G millimeter wave frequencies, a new Analog to Digital Converter (ADC), and unique discrete time analog filtering, as well as an ASIC product.

ANSYS inked a deal with Motor Design Limited to distribute the Motor-CAD tool for electric motor design and evaluation with the ANSYS electric machine design flow. Motor-CAD models can be transferred to ANSYS solvers for 2D and 3D analysis.

The microprocessor market is expected to slump this year following nine years of record-high sales, according to market research firm IC Insights. The firm sees worldwide MPU revenue dropping 4% to about $77.3 billion because of weakness in smartphone shipments, excess inventories in data center computers, and the global fallout from the U.S.-China trade war. A modest rebound is expected in 2020.

Events
Check out upcoming industry events and conferences: The System-on-Chip Conference will be at the University of California, Irvine on Oct. 16-17. The 13th IEEE/ACM International Symposium on Networks-on-Chip will be held Oct. 17-18 in New York, NY. The CASPA 2019 Annual Conference & Dinner will highlight “AI: From Silicon to Software” on Oct. 19, 12 p.m. -9:30 p.m. in Newark, CA. The AI World Conference is scheduled for Oct. 23-25 in Boston, MA, while the Linley Fall Processor Conference will take place Oct. 23-24 in Santa Clara, CA. Finishing out the month, DVCon Europe will be hosted in Munich, Germany on Oct. 30-31.



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