Author's Latest Posts


Dynamic in-chip current distribution simulation technology for power device layout design


Abstract: "This paper reports an in-chip current distribution verification technology for power devices that takes into account the effect of layout parasitics. The proposed method enables verification of dynamic current distribution in a chip considering the influence of layout parasitics from the initial stage of device development by brushing up each element technology of TCAD, Spice mode... » read more

Chip Package Co-design and Physical Verification for Heterogeneous Integration


Abstract: "Physical verification of components in 2.5D and 3D integrated chips is challenging because existing tool flows have evolved from monolithic silicon design. These components are typically designed on separate technology nodes nearly independent of each other and integrated along the design cycle. We developed an integration and verification methodology with a physical design driven... » read more

Simulation-Based Fault Analysis for Resilient System-On-Chip Design


Abstract: "Enhancing the reliability of the system is important for recent system-on-chip (SoC) designs. This importance has led to studies on fault diagnosis and tolerance. Fault-injection (FI) techniques are widely used to measure the fault-tolerance capabilities of resilient systems. FI techniques suffer from limitations in relation to environmental conditions and system features. Moreover,... » read more

Netlist Decompilation Workflow for Recovered Design Verification, Validation, and Assurance


Abstract: "Over the last few decades, the cost and difficulty of producing integrated circuits at ever shrinking node sizes has vastly increased, resulting in the manufacturing sector moving overseas. Using offshore foundries for chip fabrication, however, introduces new vulnerabilities into the design flow since there is little to no observability into the manufacturing process. At the same ... » read more

A New Multi-Stimuli-Based Simulation Method for ESD Design Verification


Abstract: "This paper analyzes TCAD ESD simulation for both HBM zapping using real-world HBM ESD waveforms as stimuli and TLP testing using square wave TLP pulse trains as stimuli. It concludes that TCAD ESD simulation using either HBM waveforms or TLP pulse trains, alone, is insufficient. We introduce a new mixed-mode simulation flow using combined HBM and TLP stimuli to achieve ESD design pr... » read more

Application and Verification of Effective Heat Spreading Angles on a Multi-Layer Thermal Design


Abstract: "When designing converters, the average junction temperature of the semiconductor is a frequently required estimate. Its analytical calculation requires the total thermal resistance of the cooling arrangement. Unfortunately, due to the complexity of the heat dissipation processes, an estimate of the thermal resistance is usually associated with low accuracy. To significantly improve ... » read more

Quantum well interband semiconductor lasers highly tolerant to dislocations


Abstract "III-V semiconductor lasers integrated on Si-based photonic platforms are eagerly awaited by the industry for mass-scale applications, from interconnect to on-chip sensing. The current understanding is that only quantum dot lasers can reasonably operate at the high dislocation densities generated by the III-V-on-Si heteroepitaxy, which induces high non-radiative carrier recombination ... » read more

HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment


Summary "To ensure secure and trustworthy execution of applications, vendors frequently embed trusted execution environments into their systems. Here, applications are protected from adversaries, including a malicious operating system. TEEs are usually built by integrating protection mechanisms directly into the processor or by using dedicated external secure elements. However, both of these... » read more

A graph placement methodology for fast chip design


Abstract "Chip floorplanning is the engineering task of designing the physical layout of a computer chip. Despite five decades of research1, chip floorplanning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts. Here we present a deep reinforcement learning approach to chip floorplanning. In under six hours, our method autom... » read more

High-Voltage, High-Current Electrical Switching Discharge Synthesis of ZnO Nanorods: A New Method toward Rapid and Highly Tunable Synthesis of Oxide Semiconductors in Open Air and Water for Optoelectronic Applications


Abstract: "A novel method of oxide semiconductor nanoparticle synthesis is proposed based on high-voltage, high-current electrical switching discharge (HVHC-ESD). Through a subsecond discharge in the HVHC-ESD method, we successfully synthesized zinc oxide (ZnO) nanorods. Crystallography and optical and electrical analyses approve the high crystal-quality and outstanding optoelectronic charac... » read more

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