Author's Latest Posts

Automation of Sample Plan Creation For Process Model Calibration
By Various Writers - 17 Jul, 2013 - Comments: 0

The process of preparing a sample plan for optical and resist model calibration has always been tedious. Not only because it is required to accurately represent full chip designs with countless combinations of widths, spaces and environments, but also because of the constraints imposed by metrology which may result in limiting the number of structures to be measured. Also, there are other limit... » read more

The Rise Of Semiconductor IP Subsystems
By Various Writers - 11 Jul, 2013 - Comments: 0

The semiconductor IP (SIP) market arose when SIP vendors created IP functions that mirrored those found in the discrete semiconductor market and made those functions available to SoC designers in the form of hard or soft SIP blocks. As the SoC and SIP markets evolved, it was a natural evolution that many discrete SIP functions be converged into larger blocks that mimic system-level functions (i... » read more

Where Should I Use Formal Functional Verification?
By Various Writers - 11 Jul, 2013 - Comments: 0

With innovations in formal technologies and methodology, the benefits of formal functional verification apply in many more areas. Although a generic awareness of where formal functional verification applies is useful, understanding the "what" and the "why" leads to greater success. Clearly, if we understand the characteristics of areas with high formal applicability, we can identify not only wh... » read more

The Integrated IP Subsystem: A Converging SoC Solution
By Various Writers - 11 Jul, 2013 - Comments: 0

The consumer device market is witnessing incredible market space convergence between mobile handheld, automotive, and home electronics. IP vendors, engineers, and system design engineers face a multitude of challenges when designing and developing ICs, systems, or subsystems for the next great portable device. The next cell phone for instance, will not only be a multimedia player, but also a de... » read more

The Rise Of Semiconductor IP Subsystems
By Various Writers - 11 Jul, 2013 - Comments: 0

The semiconductor IP (SIP) market arose when SIP vendors created IP functions that mirrored those found in the discrete semiconductor market and made those functions available to SoC designers in the form of hard or soft SIP blocks. As the SoC and SIP markets evolved, it was a natural evolution that many discrete SIP functions be converged into larger blocks that mimic system-level functions (i... » read more

RTL Design-for-Power Methodology
By Various Writers - 10 Jul, 2013 - Comments: 0

This paper presents a design-for-power methodology, beginning early in the design process at the Register Transfer Level (RTL) for maximum impact on power. To download this white paper, click here. » read more

From Design to Test: Developing High-Reliability MTP NVM
By Various Writers - 27 Jun, 2013 - Comments: 0

In developing high-quality and reliable MTP NVM, NVM IP providers must account for design and architectural considerations as well as comprehensive silicon testing. To help system-on-chip (SoC) designers select the highest reliability NVM IP, this white paper will review the key considerations involved in the entire process from design to test, including: key reliability specifications; designi... » read more

3D-IC Testing With The Mentor Graphics Tessent Platform
By Various Writers - 20 Jun, 2013 - Comments: 0

Three-dimensional stacked integrated circuits (3D-ICs) are composed of multiple stacked die, and are viewed as critical in helping the semiconductor industry keep pace with Moore's Law. Current integration and interconnect methods include wirebond and flip-chip and have been in production for some time. 3D chips connected via interposers are in production at Xilinx, Samsung, IBM, and Sematec... » read more

Extending Copper Interconnect Beyond The 14nm Node
By Various Writers - 20 Jun, 2013 - Comments: 0

Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing. To find out more about what's changing in this area and why it's so important, click here. » read more

VLSI Kyoto – The SOI Papers
By Various Writers - 19 Jun, 2013 - Comments: 0

By Adele Hars There were some breakthrough FD-SOI and other excellent SOI-based papers that came out of the 2013 Symposia on VLSI Technology and Circuits in Kyoto (June 10-14, 2013). By way of explanation, VSLI comprises two symposia: one on Technology; one on Circuits. However, papers that are relevant to both were presented in “Jumbo Joint Focus” sessions.  The papers should all b... » read more

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