Author's Latest Posts

More Efficient Design
By Various Writers - 21 Jul, 2010 - Comments: 0

Power dissipation is a major concern in modern day IC design. For wireless electronic appliances, battery life is one of the major influencers of the purchase decision and can be an effective differentiator. Mobile phones, PDAs, digital cameras and personal MP3 players are increasingly being sold on their long battery lives. In wired applications, power consumption determines heat generation, w... » read more

The Changing Supply Chain
By Various Writers - 14 Jul, 2010 - Comments: 0

By Kalar Rajendiran In efforts to improve product quality AND cut development and production costs while decreasing time to market, fabless semiconductor companies (FSCs) and OEMs have outsourced functions that didn’t add value to their products and to the company’s bottom line. Over the past 20+ years, they’ve outsourced EDA tools, test and packaging, IP core development and of course... » read more

SoC Physical Closure Begins At RTL
By Various Writers - 16 Jun, 2010 - Comments: 0

Any survey of chip design teams consistently points to two problem areas impacting quality and schedule of today's SoCs. Those areas are: a) completeness of verification, and b) physical design closure for area, timing and power for complex IP's and SoC's. With the advent of deep sub-micron technology, these problem areas have become exacerbated. In this White Paper, we take a closer look at th... » read more

Constraints Management
By Various Writers - 27 May, 2010 - Comments: 0

As the complexity of designs has scaled, the need to provide accurate physical constraints like timing, area, power and port locations has become increasingly important. Of these, timing constraints are the most difficult to provide since they depend on many external factors like floor planning, routing and integration with other blocks. Properly created timing constraints not only reduce the t... » read more

Do Your Chip A Favor: Manage The Constraints
By Various Writers - 22 Apr, 2010 - Comments: 0

A design goes through several transformations in a typical register transfer level (RTL) to layout flow, and a variety of verification techniques are employed (simulation, equivalence checking, etc.) to ensure that its intent has not changed. It’s normal for timing constraints to be created and refined in parallel with the RTL and netlist throughout the design cycle, but these constraints t... » read more

GuideWare
By Various Writers - 25 Feb, 2010 - Comments: 0

Advances in silicon technology have enabled unprecedented levels of integration in today’s SoC designs. These designs are developed through integration of various sub-systems. After the architecture and top-level micro-architecture are reasonably complete, the task of developing and integrating sub-systems begins. These sub-systems may be developed ground-up with brand new sub-system RTL. A... » read more

Smart-Grid Designs Solve Low-Power Riddles
By Various Writers - 11 Feb, 2010 - Comments: 0

By Ellen Konieczny Imagine that you go to your kitchen to get a drink and pass your home’s energy-usage monitor. Due to a recent heat wave, you see that your energy usage is already at what it usually is for the entire month. Yet you’ve still got one week left in your billing cycle. To keep the bill low, you turn your A/C thermostat up a degree and make a mental note to not keep lights o... » read more

Low-Power And RF Design Heighten Signal-Integrity Concerns
By Various Writers - 28 Jan, 2010 - Comments: 0

By Ellen Konieczny As active devices and interconnect wires shrink and are placed closer together with the march of Moore’s Law, signal integrity is becoming a huge concern. If it is not maintained, a design’s future may be marred by lower yields, unreliable performance, and failure to work efficiently—if at all. For low-power and radio-frequency (RF) designs, which are being prod... » read more

SpyGlass-CDC: Combining Structural And Functional Verification Techniques
By Various Writers - 28 Jan, 2010 - Comments: 0

Multiple, independent clocks are quintessential in SoCs and other complex ASICs today. In some cases, such as in large communications processors, clock domains may number in the hundreds. Clock domain crossings pose a growing challenge to chip designers, and constitute a major source of design errors--errors that can easily slip past conventional verification tools and make their way into sil... » read more

Automated Assembly And IP Integration Techniques For SoCs
By Various Writers - 17 Dec, 2009 - Comments: 0

Over the past few years, the consumer revolution has led to a trend in convergence of applications on a single device. The biggest example is the “ Smartphone” – handheld devices such as the iPhone or the BlackBerry that can enable consumers to read e-mail, text friends, create spreadsheets and documents, watch YouTube, play video games, listen to music, take pictures, store them, get d... » read more

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