An automated approach for memory library mapping and validation, DFT insertion, and DFT area optimization.
The use of memory-heavy IP in SoCs for automotive, artificial intelligence (AI), and processor applications is steadily increasing. However, these memory-heavy IP often have only a single access point for testing the memories. A shared bus architecture allows testing and repairing memories within IP cores through a single access point referred to as a shared bus interface. Within this interface, designers need design-for-test (DFT) tools to automatically connect to the DFT signals to apply memory BIST patterns.
In addition to automating DFT, Siemens Digital Industries Software also offers an automated approach called shared bus learning to map the physical memory composition of each logical memory and validate the cluster and logical memory library files.
Designs today contain many memory arrays, and they consume a substantial portion of the total chip area. This increase in memory size and number implies extra hardware cost for the associated memory built-in self-test (MBIST) logic. As a result, the area of the MBIST logic and the additional routing requirements may negatively impact the chip’s performance in the critical functional paths to and from memories.
A shared bus architecture provides a common access point for several memories, allowing designers to optimize routing and core performance. It also provides the flexibility to route DFT signals along functional paths behind the shared bus interface. Figure 1 illustrates a shared bus architecture containing a memory cluster module that provides access to multiple memories.
Fig. 1: Shared bus cluster in a chip.
The memories accessed through the shared bus interface are referred to as logical memories (LM_0 through LM_4 in figure 1). These logical memories can be inside or outside a cluster module. A logical memory address space is composed of one or more physical memories (PM_* in figure 1).
The embedded test hardware generated for the shared bus includes an MBIST controller, memory interfaces, and extra modules like virtual memories and glue logic. The MBIST shared bus hardware is shown in figure 2.
Fig. 2: Memory BIST shared bus hardware.
One dedicated MBIST controller is assigned per shared bus memory cluster module. The virtual memories correspond to the logical or physical memories inside the shared bus memory cluster module. Tessent MemoryBIST automatically generates a virtual memory consisting of only wires and feed-throughs to mimic the memory behavior. The glue logic controls access between the shared bus interface ports, the MBIST controller, and the virtual memories. The virtual access enables the MBIST controller to run the memory algorithms and perform standard operations on all logical or physical memories.
All the memory BIST shared bus hardware is grouped inside a wrapper module. The wrapping enables cross-boundary area optimization during synthesis and reduces the ungrouped logic in the design after synthesis. This methodology improves logic optimization and reduces area.
Tessent MemoryBIST provides an automated solution that supports mapping and validating memory library files, memory repair, complex memory configurations, and multiple ways to optimize area.
A unique feature of the tool is the ability to automate the mapping of the physical memory composition of each logical memory and validate the cluster and logical memory library files. This so-called shared bus learning flow is shown in figure 3.
Fig. 3: Overview of shared bus learning flow. TCD is Tessent Core Description.
Shared bus learning involves two key features:
P2L mapping creates wrappers by first deriving the mappings of the physical memories within a logical memory from the memory cluster RTL. Next, it populates the extracted information into the logical memory library file, also called TCD (Tessent Core Description); and finally, it writes the updated files.
Library validation verifies that:
Tessent MemoryBIST supports repairable memories with Row/Word-only, Column/IO-only, and Row/Column repair types in a shared bus cluster by inserting the required built-in repair analysis (BIRA) and built-in self-repair (BISR) logic, as shown in figure 4.
Fig. 4: Design overview of a memory cluster module with BISR.
Tessent MemoryBIST supports testing of multi-port memories within the shared bus memory cluster. It allows you to detect inter-port faults and provides flexibility to control concurrent read/write operations. The MBIST DFT insertion flow for multi-port memories is the same as single port memories.
Tessent also supports certain complex memory configurations where physical memories are larger than the logical memory. The concept of slicing a larger physical memory to fit into a smaller logical memory footprint is referred to as pseudo-vertical stacking.
Tessent MemoryBIST minimizes the shared bus test logic area by automatically reusing the memory interface logic. If identical memories in the design are not tested concurrently, then the memory interface and virtual memory are reused among the identical memories. Likewise, repair sharing can be implemented on memories with Row/Word-only, Column/IO-only, and Row/Column repair types. Memories of different dimensions can share the same BISR/BIRA hardware. Repair sharing applies the same repair information to all memories within a repair group. The designer also has control over the level of sharing or grouping of memories on a BISR/BIRA circuit to maintain a proper balance between potential yield impact and improvements in area and power-up time.
With shared bus architectures becoming more important, designers now have reliable automation to simplify the most challenging DFT tasks. Tessent MemoryBIST efficiently addresses the ever-increasing demand for testing complex memory configurations through automated support for memory library mapping and validation, DFT insertion, and DFT area optimization.
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