A new technical paper titled “Don’t CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design” was published by researchers at NYU, Intel, Duke and University of Calgary.
“To help prevent hardware security vulnerabilities from propagating to later design stages where fixes are costly, it is crucial to identify security concerns as early as possible, such as in RTL designs. In this work, we investigate the practical implications and feasibility of producing a set of security-specific scanners that operate on Verilog source files. The scanners indicate parts of code that might contain one of a set of MITRE’s common weakness enumerations (CWEs),” states the paper.
Find the technical paper here. published Sept 2022.
Baleegh Ahmad, Wei-Kai Liu, Luca Collini, Hammond Pearce, Jason M. Fung, Jonathan Valamehr, Mohammad Bidmeshki, Piotr Sapiecha, Steve Brown, Krishnendu Chakrabarty, Ramesh Karri, Benjamin Tan, arXiv:2209.01291v1.
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