Using a common access point for several memories to improve core performance and reduce cost.
New requirements in automotive, artificial intelligence (AI), and processor applications have resulted in increased use of memory-heavy IP. Memory-heavy IPs for these applications are optimized for high performance, and they will often have a single access point for testing the memories. Tessent MemoryBIST provides an out-of-the-box solution for using this single access point, or shared bus interface. This paper describes the fundamental concepts and advantages of using a shared bus architecture for testing and repairing memories within IPs cores. It also outlines key features of the Tessent MemoryBIST automation that is available from Siemens Digital Industries Software.
Shared bus interfaces and memory test
These days, designs contain a huge number of memory arrays embedded in the core, and these memories often consume a substantial portion of the total chip area. This increase in memory size and number implies extra hardware cost for the associated memory built-in self-test (MBIST) logic. In addition to the area of the MBIST logic, there may be additional costs due to increased routing. It may even negatively impact the chip’s performance in the critical functional paths to and from memories. A shared bus architecture provides a common access point for several memories, allowing users to optimize routing and core performance. In addition, a shared bus architecture provides flexibility to users to route design-for-test (DFT) signals along functional paths behind the shared bus interface. Tessent MemoryBIST instruments automatically connect to the DFT signals to apply MBIST patterns through the shared bus interface.
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