The growing number of chips in vehicles puts a spotlight on data transport architectures.
As the US is amid “Basketball March Madness” – hard to ignore when you live in Silicon Valley – it also felt like the month of “Automotive Madness.” We saw numerous announcements and events across the design chain, from semiconductor IP to software and IP providers to automotive OEMs. And in all of them, data-transport architectures, and with that networks-on-chips (NoCs), are critical.
Here are just some of the key announcements and events that happened this month:
While our Ncore Cache Coherent Interconnect IP applies to all industries that require cache coherence, Mobileye endorsed its most recent release. Leonid Smolyansky at Mobileye said, “We have worked with Arteris network-on-chip technology since 2010, using it in our advanced autonomous driving and driver-assistance technologies. We are excited that Arteris has brought its significant engineering prowess to help solve the problems of fault tolerance and reliable SoC design.”
Mobileye’s product portfolio ranges from base/enhanced advanced driver-assistance systems (ADAS) with a front camera for which a driver must be eyes-on and hands-on to the teleoperated DRIVE platform with 11 surround cameras, front Lidar, and surround imaging radars.
Besides all the computing in ADAS products like Mobileye’s, the data transport architecture has grown very complex. Just consider the inputs of the various sensors per vehicle (Source: Visual Capitalist, “Network Overload? Adding Up the Data Produced By Connected Cars.”)
That’s a total of 3-40 Gbit/s/vehicle from sensors.
On top of those, estimates for the data produced by connected cars range from as much as 450 TB per day for robotaxis to as little as 0.383 TB per hour for a minimally connected car.
As a result, OEMs need to consider carefully how to move data between different chips or chiplets within a car, as well as on systems on chips (SoCs) for which NoCs are the primary data carrier.
But wait, that’s “just” ADAS. There is more.
Inspired by Arm’s Tom Conway’s blog “Arm’s Broadest Ever Automotive Enhanced IP Portfolio Designed for the Future of Computing in Vehicles,” the illustration below shows the diversity of automotive electronics in the context of NoCs and heterogeneous integration of chiplets.
Diversity in automotive electronics.
Classic automotive low-complexity microcontrollers are typically monolithic and use non-coherent interconnect. Zonal controllers may have to share data between compute engines, especially when combining the inputs from various sensors within a zone, and therefore may use a combination of coherent and non-coherent NoCs, and their complexity often does not require distribution across chiplets. Vision-only devices will likely be primarily non-coherent as it is all about the processing of streams. If they integrate the sensor into the design, they would be a prime candidate for chiplets as they could combine different semiconductor technologies. In cockpit and IVI functions, computing the same data by different engines may require coherence, so a mix of coherent and non-coherent NoCs seems likely. Developers likely want flexibility in their portfolio management, and devices can become quite complex, making these promising candidates for chiplet-based heterogeneous integration. I already discussed ADAS and its diversity above. At its high end, it straddles what the industry often calls “data centers on wheels” or “HPC in automotive,” enabling higher autonomy levels. As with cockpit and IVI, portfolio management and complexity will make these designs more likely to be chiplet-based.
The “March Automotive Semiconductor Madness” marks just a milestone. While the automotive industry just over a decade ago seemed to be pretty slow-moving, it has today become a center of attention for semiconductors. Given the ongoing innovations in autonomy and consumers’ insatiable thirst for new and improved, safe automotive user experiences, it will likely be the center of attention for quite some time.
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