How mutation analysis can have a positive impact on the safety of your design.
Understanding verification coverage is critical for meeting IC integrity standards and goes well beyond detecting bugs in the design. Without proper verification coverage metrics, meeting strict safety standards and certification may not be achievable. Precise metrics indicate where there are gaps in verification and provide a clear view of the progress being made in the verification effort. Common simulation metrics are imprecise and only measure control coverage resulting in significant lack in verification quality. These remedial practices are time-consuming and leave undetected bugs that could significantly impact design safety. Mutation analysis takes the risk out achieving safety signoff. Results and accurate and reproduceable and creates reliable identification of verification gaps by highlighting over-constraining, dead and redundant code.
This tutorial will explore how mutation analysis can have a positive impact on the safety of your design and provide signoff confidence needed to achieve proper safety certification.
In addition, the tutorial will show how to achieve a meaningful integration of formal and simulation coverage metrics. A long-standing wish of many verification engineers and managers, coverage integration reduces effort overlap between simulation and formal, and enables faster, more rigorous signoff.
Click here to download the paper.
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