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Blog Review: Aug. 11

Burying interconnects; forksheet FETs; more bandwidth with LPDDR5X; 2.5D latch-up.

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Arm’s Rahul Mathur finds that traditional interconnects have become a bottleneck for improving IC performance and suggests buried interconnects as a way to lower signal routing delay.

Cadence’s Paul McLellan checks out forksheet FETs, a new transistor type that could allow scaling past 3nm, and the interconnect advances that will need to accompany it.

A Synopsys writer explains the new LPDDR5X standard, an optional extension to LPDDR5 to provide increased IO speed, larger die density, and data bandwidth up to 8533 Mbps.

Siemens EDA’s Dina Medhat looks at applying advanced latch-up design rules to 2.5D and 3D IC designs and key differences to be aware of.

Ansys’ Nikhil Grover explains the PCB design rules related to routing and wiring that shouldn’t be violated lest crosstalk and electromagnetic interference and compatibility issues arise.

Lam Research’s David Haynes points to the impact of specialty technologies such as MEMS, CMOS image sensors, and RF devices on everything from smartphones to COVID-19 testing.

SEMI’s Bettina Weiss listens in on a recent panel discussion to find out how members of the automotive electronics ecosystem can collaborate to address new challenges facing the auto industry.

Coventor’s Martha Lee shares some resources for aspiring MEMS designers, from university courses to short introductions.

Nvidia’s Michelle Horton checks out an effort at the University of Notre Dame to use machine learning to read and translate historical documents written in languages and styles that few people today can decipher.

And don’t miss the blogs featured in the latest Automotive, Security & Pervasive Computing and Test, Measurement & Analytics newsletters:

Siemens EDA’s Gajinder Panesar shows how to thwart hackers with security-focused embedded IP.

Flex Logix’s Andy Jaros presents a way to save power and improve performance with semi-custom chips at MCU volume prices.

Synopsys’ Dana Neustadter contends that starting security early in the design cycle is critical.

OneSpin’s McKenzie Mortensen Ross asks what you want to protect, how will you protect it, and what you stand to lose if you don’t.

Rambus’ Bart Stevens examines the varying and sometimes contradictory security requirements as an SoC moves from fab to end of life.

Cadence’s John Chawner summarizes efforts to apply computational fluid dynamics to increasingly complex aerospace applications.

Synopsys’ Rahul Singhal advises preserving the functional power intent of the design and staying within the chip power budget during testing.

Onto Innovation’s Vamsi Velidandla, Zhuo Chen, and Zhihui Jiao, and Micron’s John Hauck and Joshua Frederick examine inline CMP process control with fast throughput and higher productivity.

Siemens’ Richard Oxland observes that system-wide functional analysis helps optimize many-core SoCs and helps get them to market on time.

Advantest’s Dave Armstrong, Davette Berry, and Craig Snyder show how to optimize test efficiency and part quality by transferring some test steps from final test and burn-in toward system-level test.

FormFactor’s David Viera explains how to get lower power optical transceivers ready for the data center.

Arteris IP’s Kurt Shuler explains why collaboration between supplier and customer is key to achieving functional safety goals.

Cadence’s Sriram Sharma Kalluri reviews the basics of cryptography beyond encryption.



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