Blog Review: Aug. 2

Post-package repair; formal and machine learning; HBM2; compression; cell-aware diagnosis; testing 5G.

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In a video, Cadence’s Marc Greenberg describes the post-package repair capability in LPDDR4 and why it’s important for future LP/DDR5 memories.

Synopsys’ Kiran Vittal looks at formal, machine learning, and when computers beat humans at games.

Mentor’s Matt Knowles digs into how cell-aware diagnosis works and why it can find tricky finFET defects.

ARM’s Freddi Jeffries digs into why compression is so important for neural networks.

Rambus’ Aharon Etengoff looks at Samsung’s increase of 8GB HBM2 production and the expansion of high-bandwidth memory from graphics to data centers.

NI’s James Kimery examines some of the test challenges facing the upcoming 5G specification.

Ansys’ Kara Gremillion points to the need for simulation to help achieve the 8.8 billion miles of testing predicted necessary for autonomous cars.

In a podcast, Nvidia’s Michael Copeland chats with Andrew Ng of Deeplearning.ai, who argues that AI is the “new electricity,” and will radically change industries and become part of everyday life.

Cadence’s Paul McLellan learns all about physically unclonable functions, or PUFs, and chip-level security from Imec’s Thomas Kallstenious.

Synopsys’ Claire McKenna considers the challenges facing IoT device makers when customers prioritize convenience over security.

Mentor’s Colin Walls points out a few key concepts for designing power management software for embedded systems.

And don’t forget the featured blogs from last week’s System-Level Design newsletter:

Editor In Chief Ed Sperling contends that the saturation in the mobile market is just the beginning of the next big things.

Cadence’s Frank Schirrmeister argues that verifying entire systems will require organizational changes, not just mixed abstraction levels.

Mentor’s Dan Driscoll examines the different hardware mechanisms used for subsystem isolation in Xilinx MPSoC.

Aldec guest blogger Jim Lewis, chair of IEEE’s 1076 VHDL working group, explains why you don’t need to learn SystemVerilog.

OneSpin’s Sergio Marchese reveals how many ways there are to solve a problem.

ArterisIP’s Kurt Shuler shows how interconnect IP enables a new side view mirror technology.

NetSpeed Systems’ Rajesh Ramanujam recounts a story of physical design and a successful customer relationship.

Synopsys’ Tom De Schutter finds that as SoC designs grow larger, Chinese and Taiwanese companies are adopting integrated prototyping solutions.

ARM’s Jason Andrews digs into how to work with the latest models for software development and performance analysis.

Technical Editor Katherine Derbyshire notes that the things we take for granted are difficult for computers.

Technology Editor Brian Bailey argues that just because there are no laws protecting the privacy of most data doesn’t mean it’s okay for someone to use it.