Improving VHDL

Why you don’t need to learn SystemVerilog.


For the past several years, I have had the privilege to chair the IEEE 1076 VHDL working group. In March, we handed off the revisions to the VHDL LRM to our technical editor to finalize the document for balloting. As we are waiting for the standards process to finish up, I thought I would share my favorite new additions. Let me start with an executive summary:

VHDL-2017 plus Open Source VHDL Verification Methodology (OSVVM, gives VHDL the power, conciseness, and capability of SystemVerilog plus UVM without the complexity. If you are using VHDL, there is no compelling reason to use SystemVerilog. With my focus on testbenches and OSVVM, my favorite additions are:

  • Interfaces
  • Arrays of protected types
  • Pointers to protected types
  • Shared variables on entity interfaces
  • Generics on protected types
  • Instances of generic protected types in a shared variable declaration
  • Assert API

The top item on my list is interfaces, as it benefits RTL and testbench design. VHDL-2017 interfaces are simply a record type plus a declared mode. The declared mode allows an entire interface to be bundled into a single signal with each element having separate input/output directions (in, out, and inout). For testbenches, this simplifies writing verification components using entities and architectures, and allows a style that is either just like RTL code or simpler behavioral code.

Protected types are important to OSVVM and testbenches in general as protected types simplify the creation of data structures. OSVVM uses protected types to implement functional coverage, scoreboards, memory models, and even randomization. The first pair of extensions to protected types allow arrays of protected types and pointers to protected types. Arrays of protected types allow arrays of the data structures. Pointers to protected types allow the number of data structures in the array to be adjusted dynamically at run time. OSVVM plans to use these to create a single data structure that contains all of the coverage models within a given test. This will allow a single call to determine and/or report the status of all coverage models of a test.

The next extension to protected types allows shared variables on an entity interface. For an OSVVM-based testbench, this allows a scoreboard to be passed between the test sequencer and a model. The final extensions to protected types allows generics on a protected type and allows specification of the generics in a variable/shared variable declaration. In an OSVVM-based testbench, this simplifies the creation of scoreboards and memory models. Effectively, this makes using scoreboards, memory models, lists, and FIFOs as easy as using the built-in data structures in SystemVerilog. Do you use assert to signal errors in your testbench? Are you concerned about errors reported by the VHDL standard packages? With the VHDL-2017 assert API you will be able to get a count of these errors. Using this feature, OSVVM will be able to integrate VHDL asserts into its alert reporting structure. This is a small sampling of what is coming.

You are probably wondering why standards take so much time. VHDL standards are run by volunteers. Time is based on the number of volunteers and the amount of time they donate. We are always looking for a few more talented VHDL design, verification, compiler, and/or LRM experts to help out. If you have one of these skills and want to help, you can find us at EDAwiki.

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