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Blog Review: Aug. 4

Microprocessor challenges; connecting electrical and thermal models; AI hardware development; EMI for cable harnesses.

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Cadence’s Paul McLellan listens in as industry luminaries celebrate 50 years of the microprocessor with a discussion on major challenges to the growth of microprocessors, inflection points over the last 50 years, and predictions for the next 25.

Siemens EDA’s Vladimir Kirichenko warns that designing electrical and thermal systems separately may lead to various problems such as late design changes due to poor thermal management and points to how to connect electrical and thermal BCI-ROM models.

Synopsys’ Mike Gianfagna considers the interlinked development of AI algorithms and hardware accelerators and what the future holds for using machine learning to design better AI chips.

Ansys’ Juliano Mologni points to a way to simulate the electromagnetic interference and electromagnetic compatibility of cables, antennas, printed circuit boards, and other subsystem components involved in cable harnesses.

In a blog for Arm, Yoshinobu Nagamine of Gavi suggests ways to track vaccinations of people lacking formal identification using contactless biometric ID, as the rollout of the COVID-19 vaccine makes clear the challenges in providing and tracking even routine childhood vaccination worldwide.

SEMI’s Heidi Hoffman listens in as Glenn Snyder of Deloitte describes the state of medtech and why a combination of consumer demand and an ecosystem of bio-sensors, data standards, and regulatory improvements is setting the stage for rapid growth.

Nvidia’s Debraj Sinha points to ways edge computing and a growing number of sensors can make public spaces safer and operate more smoothly.

Plus, don’t miss the blogs featured in the latest Systems & Design newsletter:

Technology Editor Brian Bailey predicts that although COVID-19 caused many things to change, only what was rethought will survive.

Cadence’s Frank Schirrmeister explores why automatically developing the most appropriate model for a given task remains a challenge.

Imperas’ Lee Moore and Simon Davidmann contend that RISC-V verification quality is just as important as processor design freedom.

Siemens EDA’s Nebabie Kebebew shows how ML can enable fast and accurate high-sigma analysis.

Synopsys’ Manoz Palaparthi explains how to minimize unused compute resources during DRC and LVS runs.

OneSpin’s Rob van Blommestein points out that as the level of abstraction increases, so must the level of verification.

Codasip’s Roddy Urquhart foresees higher-performance RISC-V cores as barriers break down between different processor types.

Aldec’s Mariusz Grabowski shows how to integrate GNU Radio with FPGA hardware and design and verification tools.

Coventor’s Qingpeng Wang, Yu De Chen, Cheng Li, Rui Bao, Jacky Huang, and Joseph Ervin show how to improve device performance and yield at 5nm.



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