Blog Review: August 30

LLM hallucinations and EDA; PCIe 6.0 shared flow control; multi-die verification; device modeling for quantum computing; radar antennas.


Siemens’ Dan Yu examines hallucinations in large language models, the Universal Approximation Theorem, and the role they play in applying LLMs to EDA.

Cadence’s Mamta Rana introduces shared flow control in PCIe 6.0, which enables the reduced cost implementation of multiple virtual channels by allowing common sets of resources to be shared.

Synopsys’ Arturo Salz and Johannes Stahl note that while multi-die systems can follow similar verification processes as monolithic SoCs, every step must be considered from a single die to a system perspective.

Keysight’s Emily Yan argues that quantum computing could catalyze the emergence of a new market segment within the EDA industry and explains the key challenges in device modeling for quantum computing.

Renesas’ Marta Martínez Vázquez considers how to integrate an MMIC transceiver on an automotive radar module’s PCB and what should be considered to optimize the interface between the chip and the antennas.

Ansys’ Csilla Timar-Fulep dives into photoplethysmography, which uses infrared or visible range LEDs and photodetectors for optical heart rate sensors in wearable devices, and the importance of modeling human skin in creating accurate sensors.

Arm’s George Gekov demonstrates the benefits of pruning and clustering a neural network for optimization before deploying on Arm Ethos-U NPU.

SEMI’s Mayura Padmanabhan and Mark da Silva introduce the Advanced Packaging Heterogeneous Integration (APHI) Technology Community, which aims to drive awareness, adoption, and interoperability of advanced packaging and heterogeneous integration technologies.

Plus, catch up on the blogs from the latest Systems & Design newsletter:

Technology Editor Brian Bailey explains why things that did not work in the past may be the new way forward, and suggests companies innovate with help from universities.

Movellus’ Aakash Jani shows how recent technological trends have introduced uncertainties that are driving the need for a more flexible approach for mitigating on-die voltage droop.

Arteris’ Frank Schirrmeister looks at relevant source data and develops some new visualizations for SoC integration and networks-on-chip (NoCs).

Expedera’s Paul Karazuba shows why the parallel nature of transformers makes them a good fit for resource-constrained edge devices.

Keysight’s Emily Yan explores the growing impact of GaN, emerging challenges in device modeling, and how engineers could reconcile high costs with the pursuit of model accuracy.

Codasip’s Mike Eftimakis examines the facts and debunks the myths spun by RISC-V competitors about the risk of fragmentation as a weak point of the architecture.

Siemens’ Michael White explains how finding and resolving targeted issues during design and implementation helps design teams gain productivity improvements and reduce time to tapeout.

Cadence’s Reela Samuel provides an excerpt of Nimish Modi’s keynote presentation at CadenceLIVE India.

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