Blog Review: Feb. 19

RTOS interfaces; funny circuits; dessert; graphics; social media; beer; standards; always on; litho fallout; vectors; ESD; 16nm; scheduling.


Adding a GUI to an RTOS? It may sound counterintuitive, but Mentor’s Colin Walls looks at why and where they’re being used.

Cadence’s Richard Goering infuses some humor into signal integrity, which could definitely use it, courtesy of Eric Bogatin and Henny Youngman. When was the last time you saw a signal integrity engineer rolling on the floor in hysterical laughter? Well, there’s still hope—maybe at 7nm.

Synopsys’ Mick Posner is making allusions to dessert. These are not the usual images that FPGA prototypes conjure up.

ARM’s Tom Olson looks at the new Adaptive Scalable Texture Compression extension and what it means for graphics.

Mentor’s John McMillan is urging EDA engineers to jump onto social media. Some of the highly focused areas of design have been popular for some time. Where else are you going to find people to talk intelligibly about this stuff?

Cadence’s Brian Fuller has discovered an unusual video of a beer tap with a Tesla door handle (scroll way down). This gives new meaning to range anxiety.

Mentor’s Dennis Brophy looks at the new standards from IEEE and Accellera that will be discussed at DVCon next month. Bring a notebook.

Cadence’s Corrie Callenbach points to a video about always-on audio. Things will always be listening on the IoT.

And in case you missed last week’s Low Power-High Performance newsletter, here are some noteworthy blogs:

ARM’s Greg Yeric notes that with lithography scaling on hold and silicon MOSFETs losing their grip, the industry is facing some interesting challenges.

Mentor Graphics’ Marko Chew takes on vector and vectorless approaches, and where each works best.

Cadence’s Brian Fuller takes a jog through Moore’s Law and semiconductor progress in an effort to find a new runner’s watch.

Ansys-Apache’s Karthik Srinivasan finds that ESD failures can have a direct impact on first-silicon success.

Nvidia’s Barry Pangrle observes where the business is now, with an eye on where it will be when the 16nm finFET ramp begins.

Ann Steffora Mutschler examines how many power reduction opportunities are left on the table due to tight SoC schedules.

Calypto’s Qazi Ahmed notes that with hand-held devices offering everything from communications to computing the need for LP ICs has never been greater.

Jasper’s Joe Hupcey examines how Nvidia is using formal technology to reset performance.

Atrenta’s Mark Baker questions whether the ring failure at the Winter Olympics have been prevented by better verification?

Synopsys’ David Hsu says that finding low power bugs earlier in the design cycle can save big on the back end.

Leave a Reply

(Note: This name will be displayed publicly)