Blog Review: Jan. 22

Mentor’s Anil Khanna believes Nest’s approach should be incorporated into the entire power grid. The ramifications of that are interesting to ponder.

Speaking of Nest, Cadence’s Brian Fuller looks at the implications of the $3.2 billion acquisition of the company by Google. Will Google get it right? Maybe.

Synopsys’ Richard Solomon has come up with a new definition for New Year’s resolution—4K, as in screen resolution. Well, we thought it was sort of amusing. There’s a serious point in here, though, involving the I/O needed for ultra HD gaming graphics.

You can see a demo of 4K gaming in the blog from ARM’s Ellie Stone. Check out the third video from the top. When cars are finally replaced by self-driving vehicles, this may be considered historical footage.

Real Intent’s Roger Hughes digs into clock domain crossing of fast-to-slow clocks using structural and formal approaches. Clocks are a huge problem in SoCs these days. This gives new meaning to the phrase, “timing is everything.”

Semico Research’s Michell Prunty examines the good and bad of robots. Check out the video. If you dislike your neighbors, give one of these to their children, preferably before you leave on a three-week vacation.

Cadence’s Richard Goering gives a peek at what’s ahead for DVCon, a show aimed squarely at verification. Given that emulation has accounted for a big chunk of sales at the big EDA vendors, you can expect them all to be there in full force.

Mentor’s Jamie Little points to an interesting new invention: A hybrid 18-wheeler, which can trim fuel costs by up to 35%. Even better, you won’t see that plume of black smoke when they shift gears.

Synopsys’ Mick Posner teams up with colleague Eric Huang to promote their respective technologies. This is an interesting experiment in bandwidth conservation.

ARM’s Rob Coombs provides a link to a security firmware download and a video from Linaro. Take note if you work with these cores. Security already is a huge issue, and it’s only going to get larger.

Cadence’s Adam Sherer shines a spotlight, and a camera, on Freescale’s Abhinav Nawal talking about low-power verification. Anyone who thinks this stuff is easy—or even worse, can be ignored—is in for a rather rude awakening.

Mentor’s Colin Walls details three ways that embedded software can affect power, as well as the associated overhead. It’s not a simple formula, and it gets worse as you add in more power modes.

And in case you missed the most recent issue of the Low Power-High Performance newsletter, here are some blogs of note:

Mentor Graphics’ Christen Decoin looks at why effective power grid analysis will be critical to designs in Power Grid Analysis—Challenges At 20nm And Below.

Cadence’s Brian Fuller identifies Three Must-Watch Electronics Trends in 2014.

Synopsys’ Matthew Myers looks at how to add flexibility and backward compatibility to standard I/O Using USB 3.1’s Multiple INs To Reach 10 Gbps Data Rates.

Nvidia’s Barry Pangrle unearths a promising new trend involving delay insensitivity, which is moving from drawing board to real circuits in Making Waves In Low-Power Design.

Is it possible to manage power in SoC designs simply? Maybe, but as Ann Steffora Mutschler points out, Simple Does Not Mean Easy.

Atrenta’s Mark Baker argues that design tools aren’t doing their job in finding power reduction opportunities in Power Resolutions For 2014.

ANSYS-Apache’s Aveek Sarkar digs into changing requirements for design teams in Power Noise And Reliability Sign-off For The Sub-20nm FinFET Era.

Calypto’s Rob Eccles compares sequential to combinatorial optimization in Verifying Power Optimized Designs Using Sequential Analysis.