Blog Review: June 16

AMBA ATP updates; glitching chips; automotive embedded software; memory mapped registers in CXL.


Arm’s Adrian Herrera explores the latest version of AMBA ATP Engine, an open-source implementation of the AMBA Adaptive Traffic Profiles (ATP) synthetic traffic framework specification, which adds the ability to program AMBA ATP traffic generation from Linux environments.

Cadence’s Paul McLellan finds out just how effective glitching chips is by delivering incorrect voltages and clock frequencies, and the implications for security.

Siemens’ Florian Götz finds embedded software development is becoming more fundamental to today’s vehicles and looks at the process of application development and quality assurance.

A Synopsys writer looks at the difference in how memory mapped registers are placed and accessed in the CXL 1.1 and CXL 2.0 specification and explains how to access them in CXL 2.0.

Ansys’ Sean Patterson shows how high-fidelity simulation of lidar designs can provide an in-depth understanding of edge cases and assist optimization, virtual benchmarking, and package analysis.

Infineon’s Peter Friedrichs examines the interplay of failures in time rates and gate-oxide reliability in silicon carbide MOSFETs and how to screen to reduce reliability risks.

SEMI’s Heidi Hoffman surveys how companies responded to the COVID-19 pandemic, including adoption of digital technologies and what positions are still working remotely.

Applied Materials’ Regina Freed examines issues in logic cell layout optimization and pattern variability which must be addressed to enable continued improvements in logic area-cost scaling, power, and performance.

ON Semiconductor’s Oriol Fillo considers slow charging times one of the last hurdles for widespread electric vehicle adoption and looks at AC/DC conversion, calculating charging rates and times, and key aspects of fast DC charging.

Plus, catch up on the blogs featured in the latest Low Power-High Performance newsletter:

Siemens EDA’s Harry Foster points to increased design size as only one dimension of the growing complexity challenge.

Synopsys’ Gary Ruggles lays out three major changes in PCIe 6.0 that designers need to consider.

Arm’s Travis Walton and Udi Maor urge the industry to fix memory safety bugs and vulnerabilities before they become a big problem.

Rambus’ Frank Ferro explains why the same aspects that make GDDR ideal for demanding 3D graphics can boost edge inference, too.

Infineon’s Michael Ebli describes how to overcome temperature and endurance challenges in servo drive design.

Ansys’ Anthony Dawson and Jane Trenaman list reasons to integrate the simulation tools used by different teams.

Cadence’s Paul McLellan takes a look at some of the many ways to stack chips.

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