Blog Review: March 28

Formal testbench with OVL; NVDIMM; formal security; IoT labeling; eye diagrams.

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Mentor’s Joe Hupcey III and Jin Hou explain how to use the Open Verification Language (OVL) library of assertions to build an effective formal testbench.

In a video, Cadence’s Marc Greenberg discusses the benefits of moving non-volatile memory from the SSD to the DDR bus and possible new storage-class memories.

Synopsys’ Anders Nordstrom argues that security can no longer be ignored when designing SoCs thanks to Meltdown and Spectre, and says security verification must be part of the verification plan.

Aldec’s Vatsal Choksi continues his tutorial on the fundamentals of UVM with a focus on the different phases that UVM follows.

Rambus’ Aharon Etengoff checks out the UK’s plans for new cybersecurity guidelines that urge a ‘secure by design’ mindset for IoT devices as well as a voluntary labeling scheme.

Arm’s Rob Coombs shares details of the company’s Trusted Firmware M Project that aims to deliver a reference implementation of Platform Security Architecture for Armv8-M microcontrollers.

GlobalFoundries’ Gary Dagastine shares how 5G was discussed at MWC, why it will roll out differently from previous technologies, and what it means for devices and data centers.

Intel’s Garry Binder argues that the EU’s new privacy-focused General Data Protection Regulation brings with it new ways to think about security.

Ansys’ Sandeep Sovani highlights several articles on the use of simulation in developing autonomous vehicles, from radar integration to software performance.

Mentor’s Cristian Filip dives into eye diagrams and how they’re used in SerDes standards for compliance measurements.

Synopsys’ Snigdha Dua checks out the evolution of HDMI from v1.4 to v2.1 and the features that led it to become the most popular video interface.

Cadence’s Paul McLellan tells the story of JCR Licklider, one of the early pioneers of computer science in the U.S. and developer of time-sharing systems.

For more good reading, check out the blogs highlighted in last week’s System-Level Design newsletter:

Editor In Chief Ed Sperling finds commonly used metrics are taking on new meaning as electronics begin playing a bigger role.

Technology Editor Brian Bailey examines the relationship of two critical elements in chip design.

Mentor’s Stephen Pateras contends that new manufacturing and in-system test strategies are required to meet safety requirements.

Synopsys’ Kenneth Chang explains why power integrity needs to be considered much earlier in the design flow.

eSilicon’s Mike Gianfagna warns that managing the massive amounts of data generated today won’t come cheap.

Aldec’s Henry Chan shows how to use native SystemVerilog constructs as metrics for verification closure.

Cadence’s Frank Schirrmeister looks at the intersection of key industry trends at Embedded World.

OneSpin’s Sergio Marchese questions how many ways there are to solve a problem and presents the winner of the Sudoku challenge.

XtremeEDA’s Neil Johnson argues that with the upcoming Portable Stimulus standard, we need to consider whether abstraction is really the answer to everything.

NetSpeed’s Kavya Ram Mohan notes that female role models doing exceptional things in tech have always existed and hopes future generations will believe that STEM is gender neutral.



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