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Blog Review: March 3

Verification with Python; extended clock frequencies in LPDDR5X; PFM buck converter; dry resist.

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Siemens EDA’s Ray Salemi considers incrementalism in engineering, the transition from drawing circuits to writing RTL, and the next big leap of using proxy-driven testbenches written in Python.

Cadence’s Shyam Sharma looks at key changes from LPDDR5 in the LPDDR5X SDRAM standard, which extends clock frequencies to include 937MHz and 1066MHz resulting in max data rates of 7500MT/s and 8533 MT/s.

Synopsys’ Manmeet Walia and Priyank Shukla point to the importance of long-reach connectivity as hyperscale data centers transition to faster, flatter, and more scalable network architectures.

Arm’s Benoit Labbe digs into the M0N0 ultra-low-power microcontroller and the process of designing a buck converter operating primarily in pulse frequency modulation mode.

Lam Research’s Rich Wise provides an overview of photoresist and its role in the lithography process, then introduces a new dry resist technology to extend affordable and design friendly EUV patterning to future process nodes.

A Xilinx writer explains how synthesis identifies clock and other control signals when inferring a flop from Verilog RTL code.

Aldec’s Farhad Fallahlalehzari checks out why FPGAs are being used in the new Perseverance Mars rover for applications such as radar transceiver, navigation systems, motor controllers, and computer vision.

Ansys’ Jamie Gooch finds the best way to get a handle on the increasing complexity in product design is continued education, from basic engineering fundamentals to specific areas like electromagnetics.

TechSearch International’s E. Jan Vardaman warns that the shortage of substrates for IC packages is not expected to improve any time soon as price pressures and low margins have weakened substrate suppliers.

ON Semiconductor’s Deborah Herbert explains how lidar uses the direct time-of-flight technique to measure distance to objects and build a complete picture of the surroundings in a 3D point cloud and key sources of noise that create problems.

Plus, check out the blogs featured in the latest Systems & Design newsletter:

Technology Editor Brian Bailey contends that jumping straight into a discussion about implementing open-source verification tools misses one of the most important things the community could do.

Synopsys’ Qiuyang Wu warns that large size, physical reuse, and signal propagation behavior pose timing signoff challenges for AI chips.

Siemens EDA’s Joseph Sawicki shows how digital twins radically improve the speed and completeness of IC verification and validation cycles.

Cadence’s Frank Schirrmeister sketches out how digital twins are being used across the semiconductor industry, from models of SoCs to the fabs that make them.

OneSpin’s Rob van Blommestein explains how leading companies achieve IC integrity.

Codasip’s Roddy Urquhart demonstrates how using a processor description language improves the efficiency of modifying and optimizing instruction sets.



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