Blog Review: May 31

The year of 10nm; open-source silicon; security and car dongles; FPGAs and healthcare; power management.


Mentor’s Michael White predicts that 10nm will come on the scene in a big way this year with a leap to an estimated 9% foundry market share.

At the recent RISC-V Workshop, Cadence’s Paul McLellan considers whether fully open-source silicon is really viable.

Synopsys’ Robert Vamosi investigates the security risks posed by the proliferation of connected aftermarket automotive products and automakers’ mobile apps.

Rambus’ Aharon Etengoff examines what the future holds for FPGA data acceleration in healthcare.

Intel’s Ron Wilson argues for customized CPUs with a discussion of what customizations are feasible for different cases and where to start.

ARM’s John Shockley takes his home-built Raspberry Pi-based aircraft tracker out for a flight to test it under real conditions.

Semico’s Rich Wawrzyniak chats with power management architect Jawad Haj-Yihia of Sonics about today’s best practices for power management in SoCs.

Nvidia’s Jamie Beckett points to how doctors are using deep learning to predict the onset of diseases earlier.

NXP’s Ali Ors examines the way radar, lidar, and cameras are used in automotive sensing and the strengths and limitations of each.

A National Instruments writer presents recaps and videos from the annual NIWeek user conference.

Cadence’s Megha Daga dives into bandwidth requirements, one of the biggest challenges in convolutional neural networks.

Synopsys’ Eric Huang ponders the new world of robot assistants and whether they’re really necessary.

And don’t miss the blogs featured in last week’s System-Level Design newsletter:

Editor in Chief Ed Sperling digs into what multiple process nodes and market uncertainties really mean to the design world.

Synopsys’ Tom De Schutter spotlights different goals and approaches that are required for verification and validation.

OneSpin’s Dave Kelf points to various ways formal verification is deployed across the world.

Cadence’s Frank Schirrmeister looks into the key components that allow IP development in a cycle-accurate SoC context.

NetSpeed’s Rajesh Ramanujam questions whether achieving functional safety goals is possible without compromising PPA.

Mentor’s John Parry examines the role of packaging in achieving “as-designed” thermal performance.

Aldec’s Henry Chan explains why the past few months are just a blur.

ARM’s Stephen Baron provides a peek into what you’ll see next in Vulkan.

Technology Editor Brian Bailey listens in as verification execs discuss what it takes to be a successful EDA startup.

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