Blog Review: Nov. 1

DDR timing; MIPI CSI-2 v2.0; modeling serial link interfaces; security responsibilities; counterfeit auto ICs.

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Mentor’s Nitin Bhagwath continues digging into DDR timing with a look at the clock-to-DQS requirement at the DRAM and how “write-leveling” is used to solve layout issues caused by the requirement.

Synopsys’ Dipesh Handa checks out what’s new in the MIPI CSI-2 v2.0 specification that opens it up to new imaging and vision applications, including IoT and automotive.

Cadence’s Ken Willis delves into designing multi-gigabit serial link interfaces and why it’s becoming more important to move the signal integrity analysis process further upstream.

Arm’s Simon Segars argues that for a fully connected world to thrive, companies need to accept a share of the responsibility for protecting users and consider security a prerequisite to any design decision.

Rambus’ Aharon Etengoff warns that the use of stolen and counterfeit automotive ICs has increased significantly in recent years, and they’re not always easy to spot.

Marvell’s Tim Lau examines the rise of Ethernet networks in vehicles and the challenges as cars require an increasing amount of data transfer to keep up with more and more sensors.

Ansys’ Annapoorna Krishnaswamy argues that power grid design has become a limiting factor for achieving the desired performance and area targets in next generation SoCs.

GlobalFoundries’ Wallace Pai explains the company’s reasons for choosing Chengdu, China as the location for its next 300mm fab.

Nvidia’s Noah Kravitz chats with Matt Scott of Malong Technologies on why AI classification of unlabeled images is the next step for deep learning.

Cadence’s Paul McLellan highlights two presentations discussing deployment of formal technologies to verify cache-coherent protocols and a Cortex-A CPU.

Mentor’s Tom Fitzpatrick notes that only 28% of safety-critical ASIC designs achieve first-pass silicon success, and checks out how DO-254 guidelines improve the safety-critical verification process.

Plus, check out the blogs featured in last week’s System-Level Design newsletter:

Editor In Chief Ed Sperling predicts the semiconductor world is headed for some major and rapid changes.

Synopsys’ Malte Doerper zeroes in on key factors to understanding speedy virtual prototypes.

Aldec’s Vatal Choksi digs into the Universal Verification Language and how to use it effectively.

OneSpin’s McKenzie Ross shares a first-hand experience with autonomous driving, and where it falls short.

Mentor’s Ben Whitehead and Paul Morrison explain why emulation is well suited to address the complex challenges of new storage technologies.

ARM’s Zach Lasiuk shows how to streamline a software development workflow by implementing virtual platforms with regression scripting.

NetSpeed’s Rajesh Ramanujam focuses on deadlocks, which are more prevalent than anyone wants to admit, and how to deal with them.

Cadence’s Frank Schirrmeister looks back on a year of user experiences in emulation.

Technology Editor Brian Bailey asks whether technology will improve life for everyone or just a privileged few.

ArterisIP’s Kurt Shuler argues that a shift towards hardware for ADAS design could guide autonomous driving’s future.



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