Blog Review: October 18

Siemens’ Stephen Chavez suggests including analog mixed signal analysis and board level parasitics within the design process from the earliest electrical design stage and throughout final release of the PCB design.

Synopsys’ Filip Thoen, Leonard Drucker, and Vivek Prasad highlight how the complexities and interdependencies of multi-die systems create new challenges for software bring-up, and how technologies like virtual prototyping and electronics digital twins can help overcome them.

Cadence’s Veena Parthan notes that the typical capacity utilization of an enterprise data center is only 56% and looks at the use of digital twins to optimize performance and increase that amount.

Infineon’s Ashwin Kumar explains memory protection units, programmable hardware that acts as a gatekeeper of memory and enables the user to divide the memory into different regions and set memory access permissions and attributes.

The ESD Alliance’s Bob Smith chats with Scott Bibaud of Atomera about how quantum-engineered materials could improve chip performance and the steps to integrate them into the fab flow.

Ansys’ Beth Ellen Dibeler points to the value of model-based systems engineering and putting modeling at the center of more complex system designs like smart devices in consideration of design requirements, analysis, verification, and validation.

Keysight’s Alan Wadsworth explains how the digitizer mode in source/measure units (SMU) enables the capture of transient events more efficiently than using the timer trigger function and with more waveform detail.

Codasip’s Mike Eftimakis considers whether an accumulation of small innovations and continuous improvement can help limit the environmental impact of the semiconductor industry.

Arm’s Chris Goodyer introduces the first version of Arm Performance Libraries for M-series Apple silicon running macOS and for Windows 11 devices, which include key libraries for computation of linear algebra, both dense and sparse, and Fast Fourier Transforms.

Plus, check out the blogs featured in the latest Low Power-High Performance newsletter:

Rambus’ Tim Messegee looks at how the demand for more memory from data centers to endpoints is reshaping traditional architectures.

Synopsys’ Jon Ames digs into the unavoidable latency created by error correction and the physical cable length.

Arm’s Martin Weidmann provides an overview of the latest features included in the Arm ISA, from FP8 to detection of memory safety violations.

Quadric’s Steve Roddy warns that your spreadsheet of numbers doesn’t tell the whole story.

Keysight’s Gabrielle Duncan outlines the testing of the technologies reshaping cellular communication networks.

Siemens EDA’s Karen Chow and Infineon’s Susanne Lachenmann and Petya Aleksandrova look at field solvers for identifying parasitic effects.

Ansys’ Pete Gasperini explains how the placement of a phased array antenna may impact the operations of a network.

Cadence’s Veena Parthan shows how to determine lift, drag, moment, heat flux, and pressure coefficients.