Blog Review: Sept. 14

Medical device chip considerations; SystemVerilog virtual interfaces; power management for data centers.


Synopsys’ Godwin Maben, Piyush Sancheti, and Hany Elhak examine some of the top chip design considerations for medical devices and why they require careful analysis of power to reduce the number surgeries to replace batteries, reliability for devices that can be expected to last for ten years or more, and security to protect private medical data and prevent breaches.

Siemens’ Chris Spear explains virtual interfaces in SystemVerilog along with why they’re needed and examples.

Cadence’s Paul McLellan looks at the growing problem of space debris and how its creating challenges for the rapidly-increasing number of low earth orbit satellites.

Renesas’ Andrew Cowell considers the challenge created by managing the power requirements of a data center with hundreds of servers, each of which may have thousands of multi-core processors that draw hundreds of amps per core and must be turned on and off in a matter of nanoseconds.

Riscure’s Marc Witteman provides a brief explanation of the factors in choosing new cryptographic algorithms that can withstand attacks from quantum computers, and why we’re not there yet.

The ESD Alliance’s Bob Smith chats with Charles Shi of Needham & Company about whether the EDA industry can weather a downcycle, the importance of maintaining a vibrant community of small EDA companies, and expansion into new markets.

Ansys’ Kim Woodham and Laura Carter consider how simulation can help reduce the cost to produce an electric vehicle and speed up the development cycle, particularly for OEMs moving from internal combustion engines and eager to keep up the release pace set by EV startups.

A Rambus writer points to several of the most significant specification advances made in the transition from DDR4 to DDR5 DIMMs and some of the new design challenges.

Plus, check out the blogs featured in the latest Test, Measurement & Analytics and Low Power-High Performance newsletters:

Onto Innovation’s Aseem Srivastava explains why the more stringent requirements of EUV require thorough wafer inspection before the first epitaxial silicon growth step is taken.

Synopsys’ Rahul Singhal shows how streaming fabric helps deliver test data at higher speeds using only a few HSIOs.

Teradyne’s David Vondran digs into the best ways to test a mmWave beamforming module.

KLA’s John McLaughlin stresses the importance of building a strategy for sustainable and inclusive growth.

Siemens’ Martin Keim previews a new 3D-IC test solution debuting at the 2022 International Test Conference.

Siemens’ Joel Mercier and Karen Chow explain why power integrity analysis identifies key EM/IR problems in advanced node designs.

Synopsys’ Manuel Mota shows how device interoperability and UCIe enable the multi-die system market.

Fraunhofer IIS EAS’ Kay-Uwe Giering and Andy Heinig look at building the interface from quantum systems to the outside world.

Rambus’ Emma-Jane Crozier reveals how to get a glitch-free visual experience while reaching higher resolutions and refresh rates.

ClioSoft’s Amit Varde lays out a way to visualize the difference between two schematics to improve communication efficiency.

Ansys’ Christophe Bianchi examines how AI and simulation benefit engineering by turning obsolete legacy data into a high-value asset.

Cadence’s Vedansh Seth describes accurate time-stamping for a smooth communication process.

Arm’s Geof Wheelwright finds more powerful TVs create new options for delivering and consuming content.

Infineon’s Luciana Caminha Afonso digs into the unique cooling challenges in commercial vehicle electrification.

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