OSAT Consolidation Continues
By Jeff Dorsch - 14 May, 2018 - Comments: 0

Advanced Semiconductor Engineering (ASE) and Siliconware Precision Industries Ltd. (SPIL) are beginning the process of uniting the two companies, which are among the largest outsourced semiconductor assembly and testing contractors in the world. For now, the companies will continue to operate separately, while their shares are traded under the ASX symbol on the New York Stock Exchange. ASE I... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 11 May, 2018 - Comments: 0

Test and packaging In a major surprise, Cohu has entered into a definitive agreement to acquire Xcerra for approximately $796 million. With the deal, Cohu will enter the ATE market. Last year, a group from China entered into a definitive agreement under which it would acquire Xcerra. But the U.S. blocked Xcerra’s sale to the Chinese group. Ironically, at one time, Cohu was reportedly lobbyin... » read more

The Week In Review: Design
By Jesse Allen - 11 May, 2018 - Comments: 0

M&A IoT-focused memory chipmaker Adesto Technologies acquired S3 Semiconductors, a provider of mixed-signal and RF ASICs and IP. Based in Ireland, S3 Semiconductors was founded in 1986. S3 Semiconductors will become a business unit of Adesto and will continue to operate under its current model in the $35 million deal. S3 Semiconductor's parent company, S3 Group, will continue as a separate... » read more

The Week in Review: IoT
By Jeff Dorsch - 11 May, 2018 - Comments: 0

Conferences Internet of Things World 2018 takes place next week at the Santa Clara Convention Center in Silicon Valley. Executives of GE Digital, The Chamberlain Group, and UPS will be among those giving keynote addresses during the four-day conference. Monday will see pre-conference workshops, followed by three days of keynotes, presentations, and an expo floor taking in 100,000 square feet o... » read more

Higher Performance, Lower Power Everywhere
By Ed Sperling - 10 May, 2018 - Comments: 0

The future of technology is all about information—not just data—at our fingertips, anywhere and at any time. But making all of this work properly will require massive improvements in both performance and power efficiency. There are several distinct pieces to this picture. One is architectural, which is possibly the simplest to understand, the most technologically challenging to realize, ... » read more

Multiphysics Challenges For EDA Tools
By Christoph Sohrmann - 10 May, 2018 - Comments: 0

Cost and performance are the main drivers for scaling of integrated circuits. However, some applications do not scale as easily as others. This is particularly true for analog circuits and everything related to high voltage and high power. Still, the demand for these kind of applications is growing rapidly due to new emerging markets such as Industry 4.0, IoT, and e-mobility. In the automoti... » read more

Deep Learning Neural Networks Drive Demands On Memory Bandwidth
By Frank Ferro - 10 May, 2018 - Comments: 0

A deep neural network (DNN) is a system that is designed similar to our current understanding of biological neural networks in the brain. DNNs are finding use in many applications, advancing at a fast pace, pushing the limits of existing silicon, and impacting the design of new computing architectures. Figure 1 shows a very basic form of neural network that has several nodes in each layer that ... » read more

Early Chip-Package-System Thermal Analysis
By Annapoorna Krishnaswamy - 10 May, 2018 - Comments: 0

Next-generation automotive, HPC and networking applications are pushing the requirements of thermal integrity and reliability, as they need to operate in extreme conditions for extended periods of time. FinFET designs have high dynamic power density, and power directly impacts the thermal signature of the chip. Thermal degradation typically occurs over an extended period of chip operation. ... » read more

Optimizing Your DRC Debug Can Reap Big Productivity Gains
By Srinivas Velivala - 10 May, 2018 - Comments: 0

Debugging design violations found by design rule checking (DRC) has always taken a significant share of the time needed to get a design to tapeout. And debug time only increases as the number and complexity of DRC expands with each new process node. Any steps you can take to make your DRC debug process more efficient directly improves your productivity. One technique for minimizing debug tim... » read more

Developing ASIL Ready SoCs For Self-Driving Cars
By Gordon Cooper - 10 May, 2018 - Comments: 0

Artificial intelligence (AI) and deep learning using neural networks is a powerful technique for enabling advanced driver-assistance systems (ADAS) and greater autonomy in vehicles. As AI research moves rapidly, designers are facing tough competition to provide efficient, flexible, and scalable silicon and software to handle deep learning automotive applications like inferencing in embedded vis... » read more

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