Blog Review: Oct. 23
By Jesse Allen - 23 Oct, 2024 - Comments: 0

Cadence’s Sanjeet Kumar introduces the message bus interface in the PHY Interface for the PCIe, SATA, USB, DisplayPort, and USB4 Architectures (PIPE) specification, which provides a way to initiate and participate in non-latency-sensitive PIPE operations using a small number of wires. Siemens’ Dennis Brophy argues that the recently published Portable Test and Stimulus Standard (PSS) 3.0 ... » read more

Scalability of Nanosheet Oxide FETs for Monolithic 3-D Integration
By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "High-Field Transport and Statistical Variability of Nanosheet Oxide Semiconductor FETs With Channel Length Scaling" was published by researchers at The University of Tokyo and Nara Institute of Science and Technology. Abstract "We have investigated the scaling potential of nanosheet oxide semiconductor FETs (NS OS FETs) for monolithic 3-D (M3D) integration in t... » read more

Formally Modeling and Verifying CXL Cache Coherence (Imperial College London)
By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "Formalising CXL Cache Coherence" was published by researchers at Imperial College London. Abstract "We report our experience formally modelling and verifying CXL.cache, the inter-device cache coherence protocol of the Compute Express Link standard. We have used the Isabelle proof assistant to create a formal model for CXL.cache based on the prose English spec... » read more

Open-Source, Chiplet-Compatible RISC-V Controller
By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package" was published by researchers at ETH Zurich and University of Bologna. Abstract "The increasing complexity of real-time control algorithms and the trend toward 2.5D technology necessitate the development of scalable controllers for managing the complex, integrated oper... » read more

Research Bits: Oct. 22
By Jesse Allen - 22 Oct, 2024 - Comments: 0

3D-printed active electronics Researchers from MIT demonstrated fully 3D-printed semiconductor-free resettable fuses. Produced using standard 3D printing hardware and an inexpensive, biodegradable polymer filament doped with copper nanoparticles, the device can perform the same switching functions as the semiconductor-based transistors used for processing operations in active electronics. A... » read more

Review of Automatic EM Image Algorithms for Semiconductor Defect Inspection (KU Leuven, Imec)
By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "Electron Microscopy-based Automatic Defect Inspection for Semiconductor Manufacturing: A Systematic Review" was published by researchers at KU Leuven and imec. Abstract: "In this review, automatic defect inspection algorithms that analyze Electron Microscope (EM) images of Semiconductor Manufacturing (SM) products are identified, categorized, and discussed. Thi... » read more

Chip Industry Technical Paper Roundup: Oct. 22
By Linda Christensen - 22 Oct, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=371 /]   More Reading Chip Industry Week In Review AI CPU chiplet platform; Intel-AMD pact; GDDR7 DRAM; AI-RFIC funding; CHIPS Act awards; NoC tiling; thermal modeling on chiplets; $900M nuclear tech and more. Technical Paper Library home » read more

Energy Analysis: 2D and 3D Architectures with Systolic Arrays and CIM (Cornell)
By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "Energy-/Carbon-Aware Evaluation and Optimization of 3D IC Architecture with Digital Compute-in-Memory Designs" was published by researchers at Cornell University. "In this paper, we investigate digital CIM (DCIM) macros and various 3D architectures to find the opportunity of increased energy efficiency compared to 2D structures. Moreover, we also investigated th... » read more

Reactionary Or Anticipatory?
By Brian Bailey - 21 Oct, 2024 - Comments: 0

The EDA industry is located at an interesting place, where anticipation and reaction come together. Too much of either one is wasteful, but too little leaves the industry having to deal with unwanted problems. We see this happening in several areas today, and the balance is changing for several reasons. We normally expect universities to be 100% anticipatory. There is no point in them worki... » read more

Increasing Design Flexibility With RISC-V-Based Processor IP
By Rich Collins - 21 Oct, 2024 - Comments: 0

The semiconductor industry increasingly needs more flexible and scalable processor architectures, driving the growing adoption of RISC-V. Originally developed at the University of California, Berkeley, the open-source RISC-V instruction set architecture (ISA) has become very popular in recent years. RISC-V allows designers to customize their processor implementations to meet the specific needs ... » read more

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