Research Bits: June 5


Improving memristors Researchers at Los Alamos National Laboratory (LANL) have demonstrated a reliable Interface-type (IT) memristive device (memristor) that shows promise as a technique for building artificial synapses in neuromorphic computing. The team made its memristor — a component that which combines memory and programming functions — using a simple Au/Nb-doped SrTiO3 (Nb:STO) Sc... » read more

Chip Industry’s Technical Paper Roundup: June 5


New technical papers recently added to Semiconductor Engineering’s library: [table id=105 /] More Reading Technical Paper Library home » read more

The Ever-Increasing Role Of PVT Monitor IP And Its Significance In Silicon Lifecycle Management


The demand for semiconductor chips has grown exponentially over the years, driven by advancements in technologies such as artificial intelligence, the internet of things, 5G, automotive and cloud. With this increased demand, there is a growing need for more reliable semiconductor chips that can operate under extreme conditions and withstand the rigors of modern applications. Here are some of th... » read more

Framework To Compile Quantum Programs Onto Chiplets (UCSB, Cisco)


A technical paper titled "Compilation for Quantum Computing on Chiplets" was published by researchers at UC Santa Barbara and Cisco Quantum Lab. Abstract: "Chiplet architecture is an emerging architecture for quantum computing that could significantly increase qubit resources with its great scalability and modularity. However, as the computing scale increases, communication between qubits w... » read more

3D Memory Structures: Common Hole And Tilt Metrology Techniques and Capabilities


A technical paper titled "Inline metrology of high aspect ratio hole tilt and center line shift using small-angle x-ray scattering" was published by researchers at Bruker Nano and Lam Research. Abstract: "High aspect ratio (HAR) structures found in three-dimensional nand memory structures have unique process control challenges. The etch used to fabricate channel holes several microns deep... » read more

Hardware Security: Eliminating/Reducing A Blind Spot of Side Channels (CISPA Helmholtz Center for Information Security)


A technical paper titled "(M)WAIT for It: Bridging the Gap between Microarchitectural and Architectural Side Channels" was published by researchers at CISPA Helmholtz Center for Information Security. Abstract: "In the last years, there has been a rapid increase in microarchitectural attacks, exploiting side effects of various parts of the CPU. Most of them have in common that they rely ... » read more

Week In Review: Semiconductor Manufacturing, Test


Japanese and American trade officials announced a joint roadmap for cooperation in strengthening global semiconductor supply chains by advancing Japan-U.S. collaboration with emerging and developing countries in the Indo-Pacific. China and South Korea agreed to strengthen dialogue and cooperation on semiconductor industry supply chains with a focus on the supply of key raw materials and ensu... » read more

Week In Review: Auto, Security, Pervasive Computing


AI predictions and announcements filled the news this week, including a statement from the Center for AI Safety that was signed by some top AI execs — including Sam Altman, CEO of OpenAI — warning that uncontrolled AI could end up smarter than us and lead to our extinction. Foxconn estimates its artificial intelligence server revenue will double this year with the popularity of generative A... » read more

Week In Review: Design, Low Power


Arm debuted its latest platform for mobile computing. Arm Total Compute Solutions 2023 adds the new Immortalis-G720 GPU based on the 5th Generation GPU architecture, which redefines parts of the graphics pipeline to reduce memory bandwidth for the next generation of high geometry games and real-time 3D applications. The company also added two new Mali GPUs. In addition, Arm introduced a cluster... » read more

Comparing Analog and Digital SRAM In-Memory Computing Architectures (KU Leuven)


A technical paper titled "Benchmarking and modeling of analog and digital SRAM in-memory computing architectures" was published by researchers at KU Leuven. Abstract: "In-memory-computing is emerging as an efficient hardware paradigm for deep neural network accelerators at the edge, enabling to break the memory wall and exploit massive computational parallelism. Two design models have surge... » read more

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